h_a said:
Hannes, I am not a power supply expert. Can you make a reference to this cap multiplier to get this right?
I have two options I am looking at, and maybe someone can point me to the right math instructions.
I have an extra 40v+40v IE transformer sitting around. Two hots and a 0v. (Maybe F3 if I could find some Power Jfets).
My other thought is by another 18 + 18v and tweak an F4 power supply for this task. I am guessing based on my F2 power supply that changing the resistors from .47ohm to 1ohm would give me the 24v. I guess the F2 and F4 PS look quite a like anyways, with a few crosses of wires....
Mike
Alex,
Assuming you want to run the same dissipation per FET as the original circuit, changing to 35V rail would means reducing bias from 1.3A to 0.9A. You would then want to have around 3.8 to 4V across R3 & R6 depending on the actual Vgs at 0.9A of the FETs. Assuming the same first stage bias of 6mA as the original, R3, R6 should be about 650R.
Using the resistor to drop voltage for the JFETs would only work at steady state. At the moment of power-on, when there is no (transient) current through R3 & R16 as yet, the JFETs would see full rail voltage. I would use a cascode instead, e.g. ZVP3310A / ZVN3310A with the gate at +/-15V ref Gnd.
The rest looks fine to me.
Patrick
PS A separate power supply for the frontend won't be applicable here, as both drain resistors R3 / R6 that drive the second stage MOSFETs have to be second-stage rail referenced.
Assuming you want to run the same dissipation per FET as the original circuit, changing to 35V rail would means reducing bias from 1.3A to 0.9A. You would then want to have around 3.8 to 4V across R3 & R6 depending on the actual Vgs at 0.9A of the FETs. Assuming the same first stage bias of 6mA as the original, R3, R6 should be about 650R.
Using the resistor to drop voltage for the JFETs would only work at steady state. At the moment of power-on, when there is no (transient) current through R3 & R16 as yet, the JFETs would see full rail voltage. I would use a cascode instead, e.g. ZVP3310A / ZVN3310A with the gate at +/-15V ref Gnd.
The rest looks fine to me.
Patrick
PS A separate power supply for the frontend won't be applicable here, as both drain resistors R3 / R6 that drive the second stage MOSFETs have to be second-stage rail referenced.
I don't know the specifics of the F5 - have yet to get and read the article.
It was just a general suggestion, but there seem to be other things to consider as well, as Patrick suggested.
You can read about the cap multiplier - if you're still interested - in the Zen#8 and Zen#9 articles. Also an older Zen uses a cap multiplier. Just search www.passdiy.com !
Have fun, Hannes
It was just a general suggestion, but there seem to be other things to consider as well, as Patrick suggested.
You can read about the cap multiplier - if you're still interested - in the Zen#8 and Zen#9 articles. Also an older Zen uses a cap multiplier. Just search www.passdiy.com !
Have fun, Hannes
EUVL said:
To address concerns about JFET dissipation, cascoding would work,
as well as a capacitor across R16 and R17. I wouldn't worry about
these voltage figures short term.
Keep in mind that, simple as the circuit is, there are some subtle
distortion cancellations taking place. Vary the voltage, biases and
impedances, and you may take the circuit out of the "sweet spot"
and have to find it all over again.
Rendered properly, the original circuit will give you .001% to .002%
distortion at 1W / 8 ohms, but out of the sweet spot you can
expect more like .01% to .02%.
I have a follow up piece on tweaking the circuit, but it does require
a distortion analyzer.
Nelson Pass said:
Of course..
the open loop gain will be greater for the lower half (because the greater transconductance of the IRFP240) and so the closed loop gains will be slightly different. So if you closely matched the closed loop gains then it is possible to cancel some distortions.
When I tweaked the gain resistors in my simulation of the F5 I was able significantly reduce the 2nd harmonic distortion (setting R2 to 10.028 ohms or 0.3% gain error for me). But of course you can instead reduce the resistance of R1 instead, which would be easier in real life with a parallel trimpot.
But this does leave us with predominantly 3rd harmonic distortion though.
Cheers
Tim
TimS said:
You are forgetting that the average Vgs for the P channel parts is
greater, so the pot on the positive side will be higher in value already.
Don't take the sim too seriously...
And what's wrong with 3rd harmonic? I estimate that at any given
time, about 1/2 the buying public prefers 3rd over 2nd.
Nelson Pass said:
You are forgetting that the average Vgs for the P channel parts is
greater, so the pot on the positive side will be higher in value already.
Don't take the sim too seriously...
And what's wrong with 3rd harmonic? I estimate that at any given
time, about 1/2 the buying public prefers 3rd over 2nd.
Where lies the critical part corncernng the circuits sweet-spot?
Is it the current through the JFETS (8mA) or the current though the MOS-FETs (1.3A)?
Skorpio said:
Ok, Mr. Pass....I will try to be patient
http://www.firstwatt.com/articles.htm
its up
*edit* wait, sorry, that's not the tweaking article. got excited there. sorry