How to use 100 MHz OCXO for clock source
I got a low phase noise 100 MHz OCXO unit for a clock source for ES9018.
The device outputs not a square pulse but a sine wave because it is originally developed for fixed communication. The OCXO is NDK 93235D.
9325D(Fixed Communication)/OCXO (Oven-Controlled Crystal Oscillators)/NDK
Output Voltage is Min. +3 dBm.(+-1.6V p-p).
A phase noise measurement result sheet for the unit shows;
1 Hz: -73 dBc/Hz
10 Hz: -105.3 dBc/Hz
100 Hz: -139.7 dBc/Hz
1 kHz: -154.9 dBc/Hz
Its list price is about 1,000 USD.
We need a waveform shaper from +-1.6 V sine to 0-3.3 V square.
Does anyone give us a suggestion or a possible schematic for this purpose?
If you are interested in evaluating the OCXO for ES9018 clock, please let me know by private message.
As of now, I found a high-speed comparator chip, for example, NS LMH7324.
However, I'm not sure whether this one is suitable or not.
Bunpei
I got a low phase noise 100 MHz OCXO unit for a clock source for ES9018.
The device outputs not a square pulse but a sine wave because it is originally developed for fixed communication. The OCXO is NDK 93235D.
9325D(Fixed Communication)/OCXO (Oven-Controlled Crystal Oscillators)/NDK
Output Voltage is Min. +3 dBm.(+-1.6V p-p).
A phase noise measurement result sheet for the unit shows;
1 Hz: -73 dBc/Hz
10 Hz: -105.3 dBc/Hz
100 Hz: -139.7 dBc/Hz
1 kHz: -154.9 dBc/Hz
Its list price is about 1,000 USD.
We need a waveform shaper from +-1.6 V sine to 0-3.3 V square.
Does anyone give us a suggestion or a possible schematic for this purpose?
If you are interested in evaluating the OCXO for ES9018 clock, please let me know by private message.
As of now, I found a high-speed comparator chip, for example, NS LMH7324.
However, I'm not sure whether this one is suitable or not.
Bunpei
Hi Bunpei,
I have been watching your project progress, it looks awsome.
Why not just try putting the sine wave AC coupled into the chip. You can use a simple resistor divider to set the DC bias on the XI pin. Since you have to go through this pin no matter what you put in front of it, wouldn't it give a lower jitter overall? (Not retorical, im asking the question, but it my "guess" ) The tradeoff would be does a exturnal level shifter have better jitter spec than the CMOS input on the ES9018 given the slew rate of the sine wave. You can tweak the DC bias by putting a (highspeed) scope on the XI and XO, and look at the delay. Then tweak until its the shortest, this will ensure the lowest jitter possible to the inside of the chip where is actaully counts. PS, you want the posesge on the XI pin to the negedge of the XO pin delay to be the lowest. The DAC uses this edge.
Dustin
I have been watching your project progress, it looks awsome.
Why not just try putting the sine wave AC coupled into the chip. You can use a simple resistor divider to set the DC bias on the XI pin. Since you have to go through this pin no matter what you put in front of it, wouldn't it give a lower jitter overall? (Not retorical, im asking the question, but it my "guess" ) The tradeoff would be does a exturnal level shifter have better jitter spec than the CMOS input on the ES9018 given the slew rate of the sine wave. You can tweak the DC bias by putting a (highspeed) scope on the XI and XO, and look at the delay. Then tweak until its the shortest, this will ensure the lowest jitter possible to the inside of the chip where is actaully counts. PS, you want the posesge on the XI pin to the negedge of the XO pin delay to be the lowest. The DAC uses this edge.
Dustin
I never thought I could get a direct advice from Dr. Sabre!
Chiaki and I greatly appreciated your suggestion and we'd like to express our gratitude.
Yes, employing a passive voltage level shifter using a resistor divided bias seems to be the most simple and reasonable approach.
However, the quality of pull up voltage source might be critical and
a fine tuning to find the best shift level that match the actual threshold levels of DAC chip should be necessary.
Anyway, we will try it.
Thank you very much!
Chiaki and I greatly appreciated your suggestion and we'd like to express our gratitude.
Yes, employing a passive voltage level shifter using a resistor divided bias seems to be the most simple and reasonable approach.
However, the quality of pull up voltage source might be critical and
a fine tuning to find the best shift level that match the actual threshold levels of DAC chip should be necessary.
Anyway, we will try it.
Thank you very much!
This evening I preliminary connected NDK OCXO to Twisted Pear Audio Buffalo II+IVY III.
Based on Dustin's valuable advice, I adopted the easiest way.
As the output voltage range of OCXO is +-1.6V, I just concentrated on giving a necessary bias. I employed a simple UM-1 1.5 V battery for this purpose. At the same time, I also used a bunch of UM-1 batteries as +12V, -12V power supply for the OCXO.
Fortunately, the Buffalo II with standard MCU runs without any signal level tuning of the clock.
The result is marvelous! I have never listened to such a smooth and clear digital sound before. Absolutely no harshness. It is effective on both 44.1 kHz / 16 bit and 352.8 kHz / 24 bit sources. My transport is Chiaki's SDTrans192 upgraded with NDK low phase noise oscillators and RayCTech's JFET-based voltage regulators. On this condition, DXD ( 352.8 kHz/ 24 bit PCM WAV) files can be played without any noises on Buffalo II.
I'd like to express my thanks to Dustin, Russ, Chiaki, RayCTech those who created, produced and provided such great devices and products.
If any of you want to try the OCXO with your ES9018, please send me a private e-mail to bunpei<at>ta2<dot>so-net<dot>ne<dot>jp
Bunpei
I rather prefer something as tasty as vine of the village.
Last edited:
I guess Spartacus refer to the €4 of Côtes du Rhone Villages. I will take 10 of these too....
Now try running your SDTrans192 NDK from batteries to see if it's the clean PS that is giving you this performance hit or the clocks themselves? Could save you $1,000
I'm just kidding around. Good to hear about your project though, I'm sure your DAC sounds fantastic.
No problem
I can certainly supply at that price - as usual the shipping is expensive, Unless you all (y'all) want a DigiFest in central France - bring your kit; I have the analogue bits, plenty of rooms and the wine,
Now try running your SDTrans192 NDK from batteries to see if it's the clean PS that is giving you this performance hit or the clocks themselves? Could save you $1,000
I'm afraid you may have been confused with NDK crystal oscillators on SDTrans192 and NDK OCXO on Buffalo II. I compared with Crystek CCHD-950-25 on Buffalo II to NDK OCXO 9325D and I convinced that the NDK OCXO had its value.
Do you mean there is enough room to be improved on the SDTrans192 side from the view of a power supply for oscillators, apart from the Buffalo II side?
On this point, I think JFET based regulators by RayCTech have already made a significant improvement.
Yes, initially I did get confused between the 2 NDK clocks but it made me wonder how much of the improvement was coming from the battery supply to the NDK OCXO feeding the Buffalo. Did you try running the Crystek CCHD from battery to eliminate this variable?
Yes, he claims the regs sound great & better than batteries - I just wondered if you had tried batteries here also? Is the Jfet reg schema public domain?
Have you tried Salas Simplistic Shunt Low Voltage regulators?
3.3V
5V
15V example schematics. There is a trimmer for choosing Vout, make that 5k. Use 12V raw DC to feed the reg. Don't adjust less than 5V output. You can use 22uF medium esr output electrolytic capacitor in place of 2.2film + 1R output Zobel network (22uf substituting for both Zobel elements), for better general stability with unknown loads if you don't have means to check oscillations thoroughly.
Thread link: http://www.diyaudio.com/forums/powe...listic-salas-low-voltage-shunt-regulator.html
No. As I am not a battery fetishist, I do not intend to try that. I believe DAC design experts like you have already tried this and obtained enough empirical facts.
Neither for me. A SDTrans192 user tried that and reported his good result, however.
I'm not asking you to adopt batteries but you are already running the NDK OCXO on batteries & you reported the sound improved over the stock clock - I just wondered if you eliminated the batteries as the source of your improvement. Simple as that - I wasn't being smart in my last post about saving you $1,000. I don't know if battery fethist was meant as an insult but poor qusp obviously has to get his pleasure somewhere these days.
Last edited:
I did not supply a battery power to Crystek CCHD-950-25 and I have no test plan to do that because I applied the batteries to Buffalo II before and experienced a negative effect. I just used the cheapest batteries available in a local supermarket. I do believe the positive result was brought not by battery powers but by NDK OCXO with its low phase noise feature. I felt the characteristic in the sounds was something common when a low phase noise oscillator was employed.
The reason why I used the battery powers for the oscillator was that I could get a 1.5 V DC bias in the simplest way.
I should confess the description above is somewhat exaggerated.
Yesterday, I had a chance to listen to sounds of a brand new ES 9018 based DAC made by a Japanese audio vendor, Fidelix. Its type name is "CAPRICE".
The DAC has an I/V stage using a discrete JFET circuit and its sounds were very excellent. I realized an I/V stage design and implementation gave more influence on sounds than a clock source quality for ES 9018.
The Fidelix CAPRICE DAC has both preamplifier, head-phone amplifier functionality and an I2S input interface option based on LVDS standard with a HDMI connector. Clock frequency for ES 9018 is 96 MHz.
I could play 352.8 kHz/ 24 bit DXD files without noises connecting SDTrans192 via I2S on LVDS/HDMI connectors.