Clock PSU
The clock PSU is probably the most important part of the whole DAC circuit external to the DAC itself. If you get this bit wrong then your phase noise figures shown will go straight out the window. I even wager that with a really good PSU you will get better phase noise figures than those quoted.
If you're worried about PSU for the VCXO then the same worries apply to the TCXO and the OCXO.
The clock PSU is probably the most important part of the whole DAC circuit external to the DAC itself. If you get this bit wrong then your phase noise figures shown will go straight out the window. I even wager that with a really good PSU you will get better phase noise figures than those quoted.
If you're worried about PSU for the VCXO then the same worries apply to the TCXO and the OCXO.
Re: Out of band
Never heard of it. I didn't mention the manufacturer as they gave me a private quote and I didn't feel comfortable posting it here.Terry Demol[/i] WRT filtering Putzeys does point out some relevant information here: [url]http://recforums.prosoundweb.com/index.php/t/18922/0/[/url][/quote] That's the thread I referenced previously. It was pretty harsh on the marketing speak of the DAC64 web page w.r.t. the transient timing description. [QUOTE][i]Originally posted by InfiniteGain said:
Yes.
I can't remember, but it was low. It doesn't really matter for sound quality.
I think both. PM me if you want more info, since I don't want to get this thread completely off topic.
VCXO allows a short FIFO to be used when you're doing synchronous reclocking. But I'm using asynchronous USB so there's no point of the extra complexity of the supply.
-3 dB at 40 K, but it was not a steep one. In the actual implementation I intend to have a second filter after the volume control / before the output buffer.FuriousD said:
The I/V I'm using is derived from Hawksford's current feedback one, Fig.4-4. No problem such as you're suggesting showed up in the simulation, so it's clearly fast enough.
That just illustrates there isn't sufficient (or in some cases, any) filtering on inputs and outputs. I put lowpass RC filters on the input and air cored inductors on the output of the amps I've made. The only interference that I can detect audibly now is if I put the cellphone close to the input cable and use it.
I'm not using a steep filter, and I don't need it either, since the first image is at 384 kHz. And I'll easily add more poles after the I/V.
The filter doesn't have to go that low. If the interference is x dB, it doesn't mean any foldback effects will also be at x dB, so the actual analog attenuation needed is lower. Additionally, as Bruno Putzeys pointed out in one thread, the phase of the overall system can always be corrected on the digital side--meaning I don't have anything to worry about and can use strong filtering if the HF crap is too high.
In the AD9510 clock distribution IC datasheet they say fast risetimes lead to lower jitter. I suppose different input circuitry such as on a DAC chip might be more resilient but I don't know. I don't think you can go wrong with a square wave, if you keep in mind that there are very high frequency harmonics in a square wave and termination on clock lines is very important.InfiniteGain said:
Re: Clock PSU
I was going to play around (experiment first) with I/V conversion in the same manner as K&K Audio do for their RAKK DAC which is also PCM1794 based (although single chip) and uses an active tube output. Look under figure 2: http://www.raleighaudio.com/installation.htm
If results are not promising I may be forced down the op-amp route, as others have done before on this issue. There are still thermal memory issues with tubes, but these tend to be subsonic. One reason I have not looked in-depth at this yet is it is going to be relatively expensive to achieve this sort of implementation compared to using opamps.
By the way, I should have said "tube output stage" rather than "tube I/V" as I/V is still handled by a resistor or transformer.
abzug said:
I was going to play around (experiment first) with I/V conversion in the same manner as K&K Audio do for their RAKK DAC which is also PCM1794 based (although single chip) and uses an active tube output. Look under figure 2: http://www.raleighaudio.com/installation.htm
If results are not promising I may be forced down the op-amp route, as others have done before on this issue. There are still thermal memory issues with tubes, but these tend to be subsonic. One reason I have not looked in-depth at this yet is it is going to be relatively expensive to achieve this sort of implementation compared to using opamps.
By the way, I should have said "tube output stage" rather than "tube I/V" as I/V is still handled by a resistor or transformer.
I've never yet seen a simulation that does show up this problem. I like spice as a tool but my ears are far better at telling me that there is a difference. I then use Spice to try to tell me why.
If you can detect your cell phone then you have RF folddown. Either by demodulation or slew rate limiting or feedback corruption. Sorry but no amount of filtering is going to clear that away without destroying the audio band. You have to design the active electronics in a different way and then yes, shield the wotnots off it. It's no surprise that alot of the designers in Hi-Fi with new exciting product are ex RF designers.
Although that said, it is interesting that Jeff Rowland do so well in Hong Kong (the RFI capital of the world!), when they use a transformer coupled input stage and shield the nuts off their circuitry. Same difference really but introducing other issues.
You are certainly further down the road on this than anyone else I have ever spoken to.
The greatest revolution is audio will be when Power Line Communications is launched. Broadband RF on convienient antenna around your house. That should sort out the men from the boys.
Is the filter active?
I go with Occams here. The simplest solution is usually the right one. Correcting for phase in the digital domain is a lazy correction of a more serious problem.
Re: VCXO Clock
I'm using a Crystek part on the demo board right now. 49.152M. It's a two dollar part with 0.5pS typ jitter spec. I wonder how much more performance can be purchased for 50X the price?
By the way, I didn't pick that frequency for any reason other than it was the fastest Crystek osc part that I had here on hand. I don't think there is any advantage to clocking the Sabre8 at a multiple of the incoming sample rate. I will buy some faster clocks next time I make a purchase from Mouser.
FuriousD said:
I'm using a Crystek part on the demo board right now. 49.152M. It's a two dollar part with 0.5pS typ jitter spec. I wonder how much more performance can be purchased for 50X the price?
By the way, I didn't pick that frequency for any reason other than it was the fastest Crystek osc part that I had here on hand. I don't think there is any advantage to clocking the Sabre8 at a multiple of the incoming sample rate. I will buy some faster clocks next time I make a purchase from Mouser.
Uh, you asked me if I had modeled it, in post #261.FuriousD said:
- yes, but it's attenuated, and a cellphone is quite a powerful emitter
- the cellphone's antenna makes RF coupled into all parts of the circuit; on the other hand, a good PCB design will minimize loop areas so inductive coupling from the input side won't bypass the filter
- I don't know whether the I/V demodulates the signal; I was referring to an amplifier where I tested this
- a DAC is not going to put out some GHz, so again, extreme example, and my point was that it made only some audible difference (the effect of the phone on my computer sound system, however... it's close to clipping!)
Too bad Jocko's banned, as I'd love to hear his take on this...
The first filter is inside the I/V's feedback loop and so I'd call it active; it shunts the stop band to the virtual ground presented to the DAC inputs. I was considering doing a bit of prefiltering as well, but I think I'd rather avoid that as it increases the impedance the DAC sees. For the second filter, I intend to put a passive one between the volume control and output buffer.
The point is, can it work without compromising quality, and the way I understood Bruno is that it can. I'm not really looking into it for now though as I'll wait until I have a more complete hardware to measure exactly how much noise is getting through, and what distortion levels I'm achieving.
Re: Re: VCXO Clock
And that jitter figure is phase noise integrated at what offset? I bet it's at 10 kHz offset. For audio you need a comparable figure at 10 Hz offset. There's no comparison between the two. A single jitter number is absolutely meaningless without defining what it was computed over. So turn those grins upside down.rossl said:
ESS Sabre DAC Availability
I am Bryan Shaw and as Dustin mentioned previously, I am the distributor for ESS Technology in North America.
I do have availability of both eval boards and silicon. My website is not the best way to contact me as we are working out a few bugs in the submission process.
You can send me an email at bryan@shawelectronics.com or call me at (281)257-2814. I will get back to you ASAP.
Bryan Shaw
Shaw Electronics LLC.
(281)257-2814
I am Bryan Shaw and as Dustin mentioned previously, I am the distributor for ESS Technology in North America.
I do have availability of both eval boards and silicon. My website is not the best way to contact me as we are working out a few bugs in the submission process.
You can send me an email at bryan@shawelectronics.com or call me at (281)257-2814. I will get back to you ASAP.
Bryan Shaw
Shaw Electronics LLC.
(281)257-2814
I agree with abzug. The jitter spec of 0.5ps is utterly meaningless. Can you either post the Crystek part number or quote the phase noise specification. For $2 you'll be getting a pretty cheap cut of crystal with lousy close in phase noise.
Remember that phase noise on the clock close in to the carrier is vital for a high end DAC. I've ordered 3x of the 44.1584 MHz parts today, so 2x are up for grabs elsewhere if wanted. Let me know.
SuperDAC
I have gone over the Texas datsheets again and I cannot find the one that I thought allowed 32-Bit input. The Wolfson does, but the THD is not good. Have Texas changed the PCM1972/ PCM1794?
I am redoing the Matlab work on the filter to see if I can scale things to work on 24-Bits. It wont be that easy as there is no real way to tell in I2S if you have 16 or 24 bits, so we could easily waste 8-bits on zeros! I may have to include some options to select the input bit length externally. Then 16-Bit data becomes very viable for 24-Bit output.
In the absence of a Texas or AD part with 32-Bit input, the general plan is now to work with the ESS part. Ultra low noise clock PSU circuit (John Westlake has posted some good work on this), Crystek CVHD-930 as the clock part with maybe some buffering of the input data to remove the jitter. I need to read up some more on what Dustin is doing in the ESS part.
Dustin can you save me some time here and post the answer here please? Does the Sabre DAC use an internal PLL and buffer to reclock the data? does the DAC at the output clock the data out using this PLL clock or does it use the input master clock?
Filter, an improved version of that specified for the DAC64 probably implemented in DSP. If there are any DSP programmers out there who want a project, i'll provide hardware and Matlab C source and filter coeff's. My DSP implementation skills are a little lacking here.
DAC PSU will be ultra low noise. Maybe something "super-regulator" based. I need to review the options here.
Then simplest output stage possible to filter whilst avoiding the problems of RF foldown and feedback loop corruption. (Abzug if you can't see it you aren;t looking in the right place for it)
I may also include something like the Bridgeco or similar network music interface to give me access to my network music library. I had a play with the new logitech remote the other day. Damned sexy and hopefully goodnight to Sonos!
I have gone over the Texas datsheets again and I cannot find the one that I thought allowed 32-Bit input. The Wolfson does, but the THD is not good. Have Texas changed the PCM1972/ PCM1794?
I am redoing the Matlab work on the filter to see if I can scale things to work on 24-Bits. It wont be that easy as there is no real way to tell in I2S if you have 16 or 24 bits, so we could easily waste 8-bits on zeros! I may have to include some options to select the input bit length externally. Then 16-Bit data becomes very viable for 24-Bit output.
In the absence of a Texas or AD part with 32-Bit input, the general plan is now to work with the ESS part. Ultra low noise clock PSU circuit (John Westlake has posted some good work on this), Crystek CVHD-930 as the clock part with maybe some buffering of the input data to remove the jitter. I need to read up some more on what Dustin is doing in the ESS part.
Dustin can you save me some time here and post the answer here please? Does the Sabre DAC use an internal PLL and buffer to reclock the data? does the DAC at the output clock the data out using this PLL clock or does it use the input master clock?
Filter, an improved version of that specified for the DAC64 probably implemented in DSP. If there are any DSP programmers out there who want a project, i'll provide hardware and Matlab C source and filter coeff's. My DSP implementation skills are a little lacking here.
DAC PSU will be ultra low noise. Maybe something "super-regulator" based. I need to review the options here.
Then simplest output stage possible to filter whilst avoiding the problems of RF foldown and feedback loop corruption. (Abzug if you can't see it you aren;t looking in the right place for it)
I may also include something like the Bridgeco or similar network music interface to give me access to my network music library. I had a play with the new logitech remote the other day. Damned sexy and hopefully goodnight to Sonos!
abzug said:Too much trouble for me, FPGAs LOL. Sharc DSP is cheap and easy to work with.
Did you blind test it against a clock such as I mentioned?
FuriousD said:
No, I didn't blind test it against the $100 VCXO. I have had the demo board for a few weeks and don't have any $100 clocks on hand.
You may want to review all the posts in the thread. I have already replaced the 20 cent crystal on the demo board with the two dollar Crystek C3391 part. It was a great improvment. My question is... how much more improvment are you going to get by throwing money at the problem?
There are several technical problems with your suggestion, also. I don't think that the results will be that great from wiring an 80MHZ clock into a board with jumper wires. Without an unbroken ground plane and very short wires between the oscillator and the X-in pin of the DAC part, we aren't going to realize the full potential of the clock. We would also need a clean 3.3V supply delivered to the clock, and that will not be fully realized without a ground plane and good bypassing.
I would have to do a proper PCB layout to do a valid comparison.
Are you guys sugesting that the guys at ESS ship their demo boards with $100 VCXO's ???
The parts cost of the demo board, as it is, is probably less than $100. Your suggestion would more than double the parts cost of the board. At the places I have worked, such a suggestion would earn you a boot in the butt from a bean counter.
Since you have brought it up, I looked around and discovered Digikey has the fixed frequency version ( not a VCXO ) for $28.24
http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail?name=744-1055-ND
I ordered some just to test it out.
By the way, go back and look at the jitter spec on the PDF of that $100 oscillator. 12KHz.
Again you are really missing the point. Use the attached website to calculate the jitter based on the phase noise. Then you may understand a bit more of where the figure for the CVHD-930 in picoseconds comes from. I have spent a long time finding good crystals and they are very few and far between. http://www.jittertime.com/resources/pncalc.shtml
As for the other digikey Crystek crystal, you have suggested a crystal with unspecified close in phase noise, which would suggest that the curve rises upwards pretty sharply below the last data point spec'd of 1kHz. (I know this to be the case as I have data on this family from Crystek and have previously looked at them)
Crystals for Audio DAC's / ADC's have different requirements from most telecoms applications. No-one is suggesting that ESS should ship an evaluation board with a $100 crystal fitted. The eval board is supposed to show you functionally how to use the part. You can always improve in each area depending on how much you want to spend. Given the technological superiority of the ESS modulator it would make sense to see how far this can be taken.
FuriousD said:
I didn't miss the point. I fully understand the implications of the phase noise in the clock of an ASRC.
You seem to miss the point. There is no need for a $100 VCXO with this Sabre8 part.
You also seem to miss the point that very few people in this world will be willing to pay the cost for one in a consumer product.