I think there's some confusion as to the aim of my project. I'm not aiming for a high power amplifier. At the end of the day all i want is graphs matching the theory behind it, that's it and so far I'm happy with the graphs I've seen for the Half-Bridge.
I'll be more happy once i get the full-bridge out as well. But at the moment I'm mucking it up somewhere.
Sorry for my reaction, but this is really wow!
My suggestion: get rid of these comparator and schmitt triggers. This makes your circuit much more complex, and this is NOT how the education goes
Use two XOR elements to get complementary PWM and feed it into driver. Deadtime can be get using R-D circuit AFTER the mosfet driver (in series with each mosfet gate) - this is how most commercial D-amps are implemented (non UcD ). If you don't like to use separate 5v for 74hc86 XOR gates, you can use CD4000 series with the same VCC as your TL494 and mosfet driver. Please, post your complete circuit here and this will be very easy to rearrange it.
Here is the simplified class D output stage from one very known schematic of an commercial amplifier. This stage has very good timings matching and low distortions. Diodes in series with mosfet gates can be popular cheapest 1n4148. The dead time is produced because charging/opening of mosfet gate capacitance via resistor takes more time, than discharging/closing of mosfet via diode.
To make the fullbridge configuration it is needed to built one more output stage, and connect HIN and LIN inputs of second driver in parallel to the first driver, but in swapped fashion. No any additional XOR elements or invertors are needed.
Also, do not forget to post the complete schematic
Good luck!
schematic of an commercial amplifier. This stage has very good timings matching and low distortions. Diodes in series with mosfet gates can be popular cheapest 1n4148. The dead time is produced because charging/opening of mosfet gate capacitance via resistor takes more time, than discharging/closing of mosfet via diode.To make the fullbridge configuration it is needed to built one more output stage, and connect HIN and LIN inputs of second driver in parallel to the first driver, but in swapped fashion.
No any additional XOR elements or invertors are needed.Also, do not forget to post the complete schematic
Good luck!
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Thanks a lot 81bas, I might as well give this a shot.
I just went ahead with the comparator approach because of pressure for dead-time by my teacher, and this is the way he suggested. Well I've shown him it works with his way. So i got time to test out this way now.
My schematics is mostly on rough drawings in my book. I'll make a proper schematic and put it up here.
I just went ahead with the comparator approach because of pressure for dead-time by my teacher, and this is the way he suggested. Well I've shown him it works with his way. So i got time to test out this way now.
My schematics is mostly on rough drawings in my book. I'll make a proper schematic and put it up here.
That IC in your schematic will simply my life a whole lot.
I can have the entire circuitry on one supply rail then. Just a single +12V supply rail controlling everything.
Well look I see it this way ok. I've explored the way he wanted me to. And now I will compare that method with the methods provided by users who've commented here.
And I will justify to him which is better and so on, when it comes to it.
Oh man Just 3 IC's, would simply my life when i get down to the vero-board designing.
I can have the entire circuitry on one supply rail then. Just a single +12V supply rail controlling everything.
Well look I see it this way ok. I've explored the way he wanted me to. And now I will compare that method with the methods provided by users who've commented here.
And I will justify to him which is better and so on, when it comes to it.
Oh man Just 3 IC's, would simply my life when i get down to the vero-board designing.
One thing he keep whinging about is the ringing you see in the output waveform. That's why he had me do a dead-time circuit around the comparators.
That RD network is enough to avoid ringing? I mean totally or at the very least minimize it as much possible.
I remember when i implemented it in Ledmania's circuit it gave me ringing. But then again, the propagation delay on one was twice that of the other.
That RD network is enough to avoid ringing? I mean totally or at the very least minimize it as much possible.
I remember when i implemented it in Ledmania's circuit it gave me ringing. But then again, the propagation delay on one was twice that of the other.
The ringing will be present... The way to minimize it is to increase the deadtime (it is possible to increase R value in RD network, saying to 50-100 Ohm). But increasing of deadtime will increase the distortions and will decrease efficiency, so there must be a some tradeoff... The best way is to use a good PCB layout with ground plane.
Also, it is possible to have a big deadtime and low distortions too It is needed to use self oscillating topology then, which has deep negative feedback due to it's nature, and is capable to compensate the output stage distortions. The best results here are achieved using UcD topology. Or it is possible to use something like BCA. This topology has no shoot-through problems at all. These can be your next steps
Good luck!
The way to minimize it is to increase the deadtime (it is possible to increase R value in RD network, saying to 50-100 Ohm). But increasing of deadtime will increase the distortions and will decrease efficiency, so there must be a some tradeoff... The best way is to use a good PCB layout with ground plane. Also, it is possible to have a big deadtime and low distortions too
It is needed to use self oscillating topology then, which has deep negative feedback due to it's nature, and is capable to compensate the output stage distortions. The best results here are achieved using UcD topology. Or it is possible to use something like BCA. This topology has no shoot-through problems at all. These can be your next steps Good luck!
The ringing will be present...
Good luck!
Excatly Mate. I still saw ringing in the design with comparators but it was much smaller then Ledmania's schematic.
I'll compare it with the XOR scheme.
250ns Delay seems reasonable.
Ok I'm working on the schematic now (sorry for the long time I'm taking).
I attempted the XOR approach, with the IC Eva suggested and am satisfied. The signals coming out of the XOR are much cleaner then the comparator, but might just use the other IC to avoid the 5V rail.
Only problem i had is, my gate driver didn't bootstrap, but I'm not gonna bother with that for now. Some dumb mistake on my part which isn't bootstrapping it.
Would like to know how to implement deadtime otherwise though, without the schmitt trigger.
Surely the gate driver wont be happy with a exponential signal going into Hin and Lin (because of the RCD network)..lol
I've played around with comparators and building them as schmitt triggers and such on breadboard, but I've had enough. The Voltage rails of 12V, -12V, 5V, and 20V as my main supply is getting confusing now and I want to avoid it.
I just want a single 20V supply and regulate that to 12V for the electronics on the veroboard.
Please keep in mind, I'm very happy to implement just the circuits provided here, but ultimately I'm not the marker and my teacher is, hence why I have to add in dead-time, because he wants to see it in the design.
I'll post the schematic tomorrow.
I attempted the XOR approach, with the IC Eva suggested and am satisfied. The signals coming out of the XOR are much cleaner then the comparator, but might just use the other IC to avoid the 5V rail.
Only problem i had is, my gate driver didn't bootstrap, but I'm not gonna bother with that for now. Some dumb mistake on my part which isn't bootstrapping it.
Would like to know how to implement deadtime otherwise though, without the schmitt trigger.
Surely the gate driver wont be happy with a exponential signal going into Hin and Lin (because of the RCD network)..lol
I've played around with comparators and building them as schmitt triggers and such on breadboard, but I've had enough. The Voltage rails of 12V, -12V, 5V, and 20V as my main supply is getting confusing now and I want to avoid it.
I just want a single 20V supply and regulate that to 12V for the electronics on the veroboard.
Please keep in mind, I'm very happy to implement just the circuits provided here, but ultimately I'm not the marker and my teacher is, hence why I have to add in dead-time, because he wants to see it in the design.
I'll post the schematic tomorrow.
Interesting Read on this Thread
http://www.diyaudio.com/forums/showthread.php?t=112696&page=2
So because of the schmitt trigger buffers at the input of the IR2110. I can implment RCD network and have exponential signals entering the Hin and Lin.
I used Circuitmaker to figure out deadtime in my prev circuit. I never did calculations.
But are you just doing Tau = RC here?
If so isn't it 440ns not 360.
http://www.diyaudio.com/forums/showthread.php?t=112696&page=2
So because of the schmitt trigger buffers at the input of the IR2110. I can implment RCD network and have exponential signals entering the Hin and Lin.
I used Circuitmaker to figure out deadtime in my prev circuit. I never did calculations.
But are you just doing Tau = RC here?
If so isn't it 440ns not 360.
Using Circuitmaker again
I get 500Ohms and 50pF as values to get about 140nS dead-Time
So this means I'll see 140ns dead-time between Hout and Lout?
I get 500Ohms and 50pF as values to get about 140nS dead-Time
An externally hosted image should be here but it was not working when we last tested it.
So this means I'll see 140ns dead-time between Hout and Lout?
Here's my proposed schematic
http://img216.imageshack.us/img216/617/schematic.png
The values for the capacitor and resistor I need help because I do not understand the level at which the schmitt trigger buffers in the Gate Driver triggers high.
The Application Note AN-978 says this
Meaning?
If this propsed schematic works, I'm really happy because it removes the complexity of the voltage rails I have in my other approach.
Cheers..
PS. I'll Add my waveforms from the comparator approach later tonight
http://img216.imageshack.us/img216/617/schematic.png
The values for the capacitor and resistor I need help because I do not understand the level at which the schmitt trigger buffers in the Gate Driver triggers high.
The Application Note AN-978 says this
Meaning?
If this propsed schematic works, I'm really happy because it removes the complexity of the voltage rails I have in my other approach.
Cheers..
PS. I'll Add my waveforms from the comparator approach later tonight
Hi!
Why do you need to provide the deadtime BEFORE the driver? It can be done AFTER driver too: simply place the RD networks between driver and mosfets... And this should satisfy your teacher too: you will have an deadtime circuit (between driver and mosfets) and this is what he asks you for.
Also, the ringing occurs because of shoot through over both mosfets, this is obvious. And how the shoot through can occur? This happens in the following moments:
1. if both mosfets are opened simultaneously: this case is obvious and can be solved by adding of deadtime.
2. if the body diode of opposite mosfet is opened, and switching under load occurs: this happens if there is TOO BIG deadtime.
3. if mosfets are having bad dv/dt capability and/or switching occurs too fast: then switching time (ie opening time of mosfets) must be done longer by increasing of gate resistor.
So using of RD network BETWEEN driver and mosfets can solve all of these problems: this produces an adjustable deadtime, and rise/opening time is limited (because of R), whereas the fall/closing time stays at minimum (because of diode), providing better efficiency.
Bye!
Why do you need to provide the deadtime BEFORE the driver?
It can be done AFTER driver too: simply place the RD networks between driver and mosfets... And this should satisfy your teacher too: you will have an deadtime circuit (between driver and mosfets) and this is what he asks you for. Also, the ringing occurs because of shoot through over both mosfets, this is obvious. And how the shoot through can occur? This happens in the following moments:
1. if both mosfets are opened simultaneously: this case is obvious and can be solved by adding of deadtime.
2. if the body diode of opposite mosfet is opened, and switching under load occurs: this happens if there is TOO BIG deadtime.
3. if mosfets are having bad dv/dt capability and/or switching occurs too fast: then switching time (ie opening time of mosfets) must be done longer by increasing of gate resistor.
So using of RD network BETWEEN driver and mosfets can solve all of these problems: this produces an adjustable deadtime, and rise/opening time is limited (because of R), whereas the fall/closing time stays at minimum (because of diode), providing better efficiency.
Bye!
Hi!
Why do you need to provide the deadtime BEFORE the driver?
Also, the ringing occurs because of shoot through over both mosfets, this is obvious. And how the shoot through can occur? This happens in the following moments:
1. if both mosfets are opened simultaneously: this case is obvious and can be solved by adding of deadtime.
2. if the body diode of opposite mosfet is opened, and switching under load occurs: this happens if there is TOO BIG deadtime.
3. if mosfets are having bad dv/dt capability and/or switching occurs too fast: then switching time (ie opening time of mosfets) must be done longer by increasing of gate resistor.
So using of RD network BETWEEN driver and mosfets can solve all of these problems: this produces an adjustable deadtime, and rise/opening time is limited (because of R), whereas the fall/closing time stays at minimum (because of diode), providing better efficiency.
Bye!
He said something about current flowing back into the gate driver, because of the diode in parallel.
But in all honesty I didn't understand what he was talking about.
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