Hi David
I am not familiar with the 6000 amp circuit but I agree it is important to have enough class A drive current to charge and discharge the output mosfets for the worst case current slew expected. In my latest amp I use an EF driver stage with 40mA bias (a modified HEC gate drive scheme). I used Q-fet verticals. It was a curiosity experiment that went very well indeed.
Each fet gate in the pair is essentially driven by independent output Z from the driving stage because for N-ch and P-ch of matched Gm the P-ch may have 2X the input capacitance of the N-ch. It seems that being able to use the input capacitance of the output fets to set the dominate pole is another advantage of lateral fets over verticals I've never considered. For the planer stripe DMOS from Fairchild, AKA Q-fet vertical type fets, as the device approaches saturation with a Vds of a couple of volts, Coss (Cds + Cdg) becomes dominate. Typical descrete pluaral well die structure such as Hexfets seem to have CISS dominate but COSS is significant at Vds saturation. I do not believe this is the case with the lateral structure.
CBS240,
as pointed out, the input capacitance stays pretty constant independently of structure. Cgs is large even for laterals, unfortunately, it cannot be made very small as it acts as charge storage required for operation. For linearity, however, a low Vgsth and a small Cgd are of primary importance.
Coss, a junction capacitance (like any capacitance, independently of structure) increases with decreasing voltage, having its highest value at Vds zero.
It`s normal.
as pointed out, the input capacitance stays pretty constant independently of structure. Cgs is large even for laterals, unfortunately, it cannot be made very small as it acts as charge storage required for operation. For linearity, however, a low Vgsth and a small Cgd are of primary importance.
Coss, a junction capacitance (like any capacitance, independently of structure) increases with decreasing voltage, having its highest value at Vds zero.
It`s normal.
True but if you are using the input capacitance as the compensation, vertical fet COSS is almost equal or can be even greater than CISS at saturation. Check the datasheet. Since CISS and COSS is essentially in paralell to the AC world it may cause the pole to shift. I question using the input capacitance as compensation with vertical fets. COSS is important in switching applications which is what vertical fets are designed for. CISS is essentially bootstrapped as seen by the driving stage when used as a source follower significantly reducing it's effect but COSS is not. COSS is quite a bit lower except during Vds saturation. Lateral fets typically have much less Cdg and Cds. CISS and COSS for a vertical P-ch fet may exceed 5nf each at 1Vds and the larger Gm of the device allows for that operating condition even under load. As for linearity, the capacitances of any mosfet is quite non-linear not to mention Id vs Vgs. IMHO, I would not build a mosfet amp without some sort of local error correction to straighten that out so as the global loop would not have to deal with it. Bad juju to have significant non-linearities within a long FB loop not to mention the phase shift of the input capacitance and the gate stopper denigrating the overall phase margin. Local compensation at the device can help with that. Some folks believe that FB cancels non-linearities but that is not exactly true. Lateral fets are much more linear than verticals as verticals are really designed for switching and the datasheets signify this. I don't think lower Vgsth is related to linearity as much as Vgs relationship to Id which is dependent on Gm.
I agree with your first comment about Vertical FETs. These are totally different devices. Vertical and Lateral MOSFETs should never be veiwed as in any way interchangable. But the original post is specifically about Lateral FETs and my previous comments were restricted to Lateral FETs.
I struggle a bit with your second comment however... that error correction is always needed with MOSFET power amp stages - if you mean lateral devices also. The Hitachi devices have a temperature coefficient function that is positive at low currents but negative at higher currents - the transition occurring at an order of a few hundred milliamps. This is perfect for class AB amps, but means that a typical class AB output stage with these devices will settle down at a quiescent current somewhat higher than in a bipolar design. At these quiescent currents the output stage using lateral devices will generate only in the order of 0.1% THD, requiring only 20db of either local of global feedback to get to an order of 0.01%. Once at these distortion figures the sound of the amp will be dependent on far more subtle things that can be revealed by simple THD measurements - and this is where the fun begins
Philosophically I prefer to minimise the number of stages in the signal path so that the design is as simple as possible. I am not into simplicity for the sake of it, and I am perfectly happy to through scads of devices at a problem, if that is what it takes to fix it. But I prefer to minimize the number of gain blocks in the signal path. In the end I guess it is a personal design choice
very best wishes
Dave
output stage temperature compensation
For the output stage with power BJT (like Thermaltrak and else) we see attempt to improve the temperature compensation for quiescent current. It seems that for Lateral mosfet most designs only rely on the negative coefficient for protection without any special care to accurately have the bias current stable. Any comments on that?
Thanks
Fab
For the output stage with power BJT (like Thermaltrak and else) we see attempt to improve the temperature compensation for quiescent current. It seems that for Lateral mosfet most designs only rely on the negative coefficient for protection without any special care to accurately have the bias current stable. Any comments on that?
Thanks
Fab
CBS240,
Vgsth must be small to assist input signal linearity (lower drive voltage amplitude) and flat characteristics over a wide range of gate voltage. In this regard a span of several volts is huge. Also, a higher gate voltage means higher gate charge, higher Coss and lower Rdson - negative factors for linearity.
Vgsth must be small to assist input signal linearity (lower drive voltage amplitude) and flat characteristics over a wide range of gate voltage. In this regard a span of several volts is huge. Also, a higher gate voltage means higher gate charge, higher Coss and lower Rdson - negative factors for linearity.
fab,
in the case of bipolar transistors, Gm increases with increasing temperature and Ic varies exponentially with temperature, in the case of lateral MOSFETs, the (low) Gm decreases with increasing temperature and the (high) Rdson increases with increasing temperature, so they protect themselves very well.
in the case of bipolar transistors, Gm increases with increasing temperature and Ic varies exponentially with temperature, in the case of lateral MOSFETs, the (low) Gm decreases with increasing temperature and the (high) Rdson increases with increasing temperature, so they protect themselves very well.
I know about Lateral "self" protection. My question is more about the accurate control of bias current against temperature variation.
thanks
I do not believe Vgs threshold has much to do with linearity, and Rdson is irrevelent to linear amp OPS because 99% of time you are not even close to full Rdson. Rdson is indicative of Gm though and is obviously significantly different between the two types of devices. Laterals have low Vgsth, less than 1V. Vertical fet Vgsth is ~4V. A comparison of Vgsth vs linearity is to compare different devices, like comparing apples to oranges. A better comparison would be Vgs vs Id. Lateral Vgs vs Id tends to adhere to the square law. This may be the reason for the 'sound' of laterals and why folks prefer them. Vertical fet Vgs vs Id is more of an exponential function. Don't let the low Vgsth of laterals mislead, due to thier much lower Gm they require quite a bit more Vgs to conduct higher currents. For example, a 2SK1058 has a Vgsth of 0.7V. At Id=7A Vgs is 8.3V, a difference of 7.6V! IRFP240 has a Vgsth of ~4V and at Id=7A Vgs is only about 5.5V, a difference of only 1.5V. This is one reason common source OPS is popular with lateral fets. Before the action of FB the lateral fet looses a lot of signal magnitude at peak currents in SF configuration. This is the reason for SF topology I would use EC for laterals as well not so much the capacitance issues, rather the load dependent change in Vgs. I'm not advocating one device or the other, just point out that even though the input capacitance (dominated by Cgs) is greater with verticals, laterals require a much larger change in Vgs vs Id so the actual charge required may be less but by not that much for lateral than for vertical. There are other reasons that have been pointed out which make laterals more suitable for linear amp OPS. Another reason is because the lateral fet Gm is significantly lower, its effective Ft is also lower; Ft=Gm/(2*pi*Cin). This makes them a little easier to stabilize.
Do you mean controlling the VAS current using temperature sensing of output devices? If so ,do you have an example of such circuit?
What is the advantage compared to have a voltage multipler using a Lateral Fet (for output biasing purpose) that would follow a similar current/temperature curve as the Lateral output devices?
Thanks
Fab
CBS240,
a large (nominal) value of Rdson and large channel resistance are basic conditions for linear transconductance. Vgsth and input signal excursion needs to be small in the used area, this generally applies to all kinds of amplifying device in any configuration and should make sense to you. It is much harder to obtain flat characteristics over a wide range.
Furthermore, a short channel length is highly desirable. It´s certainly not a problem to make short channel devices, but a precise control of short channels expressly is, the narrow lateral structure is superior in this regard. For switching devices, saturation mode properties are not of interest, a linear transconductance would be a nuisance as it essentially obstructs the switching performance.
We need a transconductance that is linear, not high and nonlinear. High Gm, high Idss and low Rdson bring about severe nonlinearities and nasty capacitances. The transconductance of verticals is generally excessive for audio.
Kind regards.
a large (nominal) value of Rdson and large channel resistance are basic conditions for linear transconductance. Vgsth and input signal excursion needs to be small in the used area, this generally applies to all kinds of amplifying device in any configuration and should make sense to you. It is much harder to obtain flat characteristics over a wide range.
Furthermore, a short channel length is highly desirable. It´s certainly not a problem to make short channel devices, but a precise control of short channels expressly is, the narrow lateral structure is superior in this regard. For switching devices, saturation mode properties are not of interest, a linear transconductance would be a nuisance as it essentially obstructs the switching performance.
We need a transconductance that is linear, not high and nonlinear. High Gm, high Idss and low Rdson bring about severe nonlinearities and nasty capacitances. The transconductance of verticals is generally excessive for audio.
I don`t think this equation holds. Things are very much more complicated than that.
Kind regards.
one more question
It seems to me there’s one more rather interesting question. I mean does the considering VAS with the collector feeding FET output stage provide good control of this stage and, hence, a good control of speakers? Sure, the common feedback also takes part in the control of output stage, but is it enough to obtain good dynamics of sound?
It seems to me there’s one more rather interesting question. I mean does the considering VAS with the collector feeding FET output stage provide good control of this stage and, hence, a good control of speakers? Sure, the common feedback also takes part in the control of output stage, but is it enough to obtain good dynamics of sound?
the nearly infinite input impedance allows a vigorous transfer of voltage. At high frequencies the input capacitance messes up the impedanc
My respect and thanks for replay to Wu Yit.
Yes, i agree with you, the topology discussed provides good transfer of voltage. But what would happen if the load (speakers) starts to change the voltage on the source pin of output follower FET? Would the voltage on the gate pin remain the same or wood it change too for VAS can’t maintain its own output voltage?
Of course, all this details may not be significant as concerning HI-FI audio, but they can cause the difference between HI-FI and HIGH-END sound. Although it’s only my own opinion based on some experiments with topologies discussed.
My respect and thanks for replay to Wu Yit.
Yes, i agree with you, the topology discussed provides good transfer of voltage. But what would happen if the load (speakers) starts to change the voltage on the source pin of output follower FET? Would the voltage on the gate pin remain the same or wood it change too for VAS can’t maintain its own output voltage?
Of course, all this details may not be significant as concerning HI-FI audio, but they can cause the difference between HI-FI and HIGH-END sound. Although it’s only my own opinion based on some experiments with topologies discussed.
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