Theres a lot of us that know nowt them in't there lad.
Personaly I'll admit to being a bit of a thicko when it comes to this digital stuff, not knowing my velocity factor from my monotonic signal, and believing electrons only travel at less than a tenth of a milimeter per second, and always mistaking my Ott for a Johnson, so I bow to you greater knowledge and await with baited breath for the next revelation in this road to physics nirvana.
Qusp, have you not read the link to Mr Colloms revealing article, from it I deduce that somehow the system knows when it is moving audio bits, as compared to the millions of boring non-audio bits, how could I have been duped for so long, in believing in digital transfer being so reliable, when these sneaky audio bits now pick up detrious on their way around the system.
Personaly I'll admit to being a bit of a thicko when it comes to this digital stuff, not knowing my velocity factor from my monotonic signal, and believing electrons only travel at less than a tenth of a milimeter per second, and always mistaking my Ott for a Johnson, so I bow to you greater knowledge and await with baited breath for the next revelation in this road to physics nirvana.
Qusp, have you not read the link to Mr Colloms revealing article, from it I deduce that somehow the system knows when it is moving audio bits, as compared to the millions of boring non-audio bits, how could I have been duped for so long, in believing in digital transfer being so reliable, when these sneaky audio bits now pick up detrious on their way around the system.
If I was wrong that you were deliberately misrepresenting things rather than simply not understanding the basics, I apologize.
might be something else, it really has the affection while we tested in customers lab, CAT5 and CAT7 cable sounds different with our FIFO buffered digital circuit.
we did wanna open source and share with ppl here in the very beginning, but our customer push us to make this product better and better, so, I'm replying in a different way later, but reply here again just to keep promise for the free samples.
this project is complicated, including schmetic, pcb layout (5 pcbs in the products), linux OS driver, Uboot, audo decoder, UI, UPNP protocol(intel always think in a hardware way, the documents they provided sucks), MCU program, DSP, verilog....
so, open source makes no sense and few ppl could do, also, too many factors to make it good...
we do have latest model setup under request of our OEM customers, but need to test, especially by top recording engineers. when they agree, we make it.
it seems the words 'the standard model' have not even got meaning in this brave new world?
@ Marc, yes I only just read the thread mentioned... lol, yeah now thats science! I guess they can rest their case now? of course its predictable that only the audio electrons are encouraged to behave this way....
@ Marc, yes I only just read the thread mentioned... lol, yeah now thats science! I guess they can rest their case now? of course its predictable that only the audio electrons are encouraged to behave this way....
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On a more scientific note Qusp, wots on your cats head, a kermit hat?
DF96, there are no books, tomes, white papers (apart from Andrex), or other documentation for new age electronics, information can only be picked up by intense meditation tuning into the extreme concentration of an audiophile listening (with the intensity of the constipated trying to pass go) for the latest fad that is ruining there listening pleasure.
I would love to know what they have done with the layout, if anything that is so special and will encourage them electrons to crawl there way around the traces at barley 0.1mm per second, me when using intel chips I defer to their very comprehensive layout guides, same with xylinx micron etc etc etc.
Sorry if I sound bitter, but I have to face another week away from home and my employers have downgraded my hotel room, most prisoners have more room and a bigger tele, well cant do enough for a good firm wot!
Bitter Twisted...
DF96, there are no books, tomes, white papers (apart from Andrex), or other documentation for new age electronics, information can only be picked up by intense meditation tuning into the extreme concentration of an audiophile listening (with the intensity of the constipated trying to pass go) for the latest fad that is ruining there listening pleasure.
I would love to know what they have done with the layout, if anything that is so special and will encourage them electrons to crawl there way around the traces at barley 0.1mm per second, me when using intel chips I defer to their very comprehensive layout guides, same with xylinx micron etc etc etc.
Sorry if I sound bitter, but I have to face another week away from home and my employers have downgraded my hotel room, most prisoners have more room and a bigger tele, well cant do enough for a good firm wot!
Bitter Twisted...
I read your post to mean that in all cases there is a buffer prior to the DAC so therefore spdif (for example) induced jitter doesn't matter to any DAC. If you meant that jitter arising earlier in the chain is eliminated by a buffer then I can see no logical reason why you are incorrect.
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Here's a couple.
This is partially correct. That's one element of the system. So is the local clock for the DAC (the bit that Guido sells).
No I was saying that only jitter that apears in the last satge of the digital data's transprot from long term storage device to DAC matters, this is more often and not the SPDIF interface.
Concentrate on the last step, and if it is of concern isolate and buffer the data, then you can optimise the timing, minimise noise from a PC (cos whotever you try the only way of cutting down a digital systems noise is reducing the switching speeds and thus minimising switchig noise of the gates, oh and nice slooooow rise times, Olivetti 24 anyone, we could argue over the difference then between 5.25 discs and 3 and a bit).
Thats why we have so many voltages on PCB's involving processors, CPLD's, FPGA's etc, they cant swing 5V any more, its all this sill 45nm and smaller features and silly rise times to allow double data rate memory to work (never mind burst mode) and such like.
Concentrate on the last step, and if it is of concern isolate and buffer the data, then you can optimise the timing, minimise noise from a PC (cos whotever you try the only way of cutting down a digital systems noise is reducing the switching speeds and thus minimising switchig noise of the gates, oh and nice slooooow rise times, Olivetti 24 anyone, we could argue over the difference then between 5.25 discs and 3 and a bit).
Thats why we have so many voltages on PCB's involving processors, CPLD's, FPGA's etc, they cant swing 5V any more, its all this sill 45nm and smaller features and silly rise times to allow double data rate memory to work (never mind burst mode) and such like.
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