Enclosed you will find the simulation of a simple carrier-based amp with feedback-takeoff from the filter (of course) and a (deliberately low !!!!) switching frequency of 250 kHz.
As comparator/output stage I used the aforementioned "etable" from PSPICE.
NFB is 20 dB up to approx 10 kHz, where it starts to drop wit 6 dB/octave, reaching the unity-gain point at 100 kHz approx.
The overall cutoff frequency is around 45 kHz. k3 is slightly below 0.1%. But it has a little high k5 and k7.
Regards
Charles
As comparator/output stage I used the aforementioned "etable" from PSPICE.
NFB is 20 dB up to approx 10 kHz, where it starts to drop wit 6 dB/octave, reaching the unity-gain point at 100 kHz approx.
The overall cutoff frequency is around 45 kHz. k3 is slightly below 0.1%. But it has a little high k5 and k7.
Regards
Charles
Hi Charles,
I think it is nothing unusal that you have such a large gain in AC analysis with your circuit. I think spice uses full gain of your Etable element when setting operational point for AC analysis, where gain in fact should be Vlim/Vramp. I will try to find and post some links for averaged models for carrier based PWM stages, but I would still like to know how AC model for hysteretic type oscillator would look like. Maybe this link would be a first starting point.
Best regards,
Jaka Racman
I think it is nothing unusal that you have such a large gain in AC analysis with your circuit. I think spice uses full gain of your Etable element when setting operational point for AC analysis, where gain in fact should be Vlim/Vramp. I will try to find and post some links for averaged models for carrier based PWM stages, but I would still like to know how AC model for hysteretic type oscillator would look like. Maybe this link would be a first starting point.
Best regards,
Jaka Racman
I'm packing for a week off and doing some other stuff...
In short, the gain of a self-oscillating power stage calculates similarly to that of a fixed frequency one. The patent shows how to transplant the reasoning used on fixed frequency amps onto the self-oscillating one. There's a slight error in the maths, the actual gain equation is significantly more elegant, as I hope you'll find out.
Point is, the carrier imposes a certain dvdt on the comparator input at the zero crossings. An input voltage is converted to a switching time change as per the dvdt.
In short, the gain of a self-oscillating power stage calculates similarly to that of a fixed frequency one. The patent shows how to transplant the reasoning used on fixed frequency amps onto the self-oscillating one. There's a slight error in the maths, the actual gain equation is significantly more elegant, as I hope you'll find out.
Point is, the carrier imposes a certain dvdt on the comparator input at the zero crossings. An input voltage is converted to a switching time change as per the dvdt.
The gain from the modulator to the output of the switching stage is determined by
A = (output-stage supply-voltage)/(peak voltage of triangle)
The combined gain of a hysteresis-controlled modulator & output stage is determined by
A = (output-stage supply-voltage)/(0.5 * hysteresis-voltage)
In both cases a half-bridge is assumed, for full-bridge it is twice as much.
If you run AC analysis you best model the whole as a voltage-controlled voltage source with gain A determined with the above formulae.
Regards
Charles
A = (output-stage supply-voltage)/(peak voltage of triangle)
The combined gain of a hysteresis-controlled modulator & output stage is determined by
A = (output-stage supply-voltage)/(0.5 * hysteresis-voltage)
In both cases a half-bridge is assumed, for full-bridge it is twice as much.
If you run AC analysis you best model the whole as a voltage-controlled voltage source with gain A determined with the above formulae.
Regards
Charles
Hi Charles!
Yes, I see the same.
My personal favourite to simulate is the ideal gain device.
I use the voltage controled voltage source only if I need isolation between output and input.
But I am wondering if pspice is able to notice gain A in the correct way as described by you, if it has to caculate a switching bridge (not modeled as a gain or voltage-voltage-source), but AC analysis is chosen....
Couldn't it happen that PSPICE simply calculates the linear small signal forward gains of each stage, without taking care about hysteresis and DC rail? From which caculation (except transient) can PSPICE notice the value of hysteresis...?????
Bye
Markus
Yes, I see the same.
My personal favourite to simulate is the ideal gain device.
I use the voltage controled voltage source only if I need isolation between output and input.
But I am wondering if pspice is able to notice gain A in the correct way as described by you, if it has to caculate a switching bridge (not modeled as a gain or voltage-voltage-source), but AC analysis is chosen....
Couldn't it happen that PSPICE simply calculates the linear small signal forward gains of each stage, without taking care about hysteresis and DC rail? From which caculation (except transient) can PSPICE notice the value of hysteresis...?????
Bye
Markus
inside PSPICE...
Hi Kanwar,
I opened my thread about my babysteps of my Class D Rookie... Well... had some drawback, because I fried my hard disc by a short circuit from my 2kVA PSU ==> USB scope ==> internal GND of notebook ==> hard disc ==> enclosure of hard disc ==> screw at hard disc cover ==> metal rack on which the notebook was standing (while I thought it would be floating well isolated...
) ==> PSU...
OK, only the hard disc was fried, all the rest of the notebook seems to fine. ..running again.
I went on and since about one month I am strugling with the weaknesses of the IRS20954S. It is oversensitive vs noise. I managed to get it working up to something about 40A..50A even with the noise at hard switching conditions. But I wanted to have proper operation up to 60A..70A (did not work out so far) and then set the current limit to 55A. Furtheron the IC can be killed by the MosFets reverse capacity. I was able to cure this by an external driver.... STOP !!! Too many work arounds and still no satisfying behaviour. I think now I know why IR does promote this IC just for 200W, while the voltage rating and 1A driver capability in the data sheet would indicate to use it also in higher power amps...
I am right now changing my concept to:
Hysteresis resonator + level shift towards neg rail + IR2113 halfbridge driver + discrete shut down circuit
Will post the new schematic soon in my babystep thread.
Bye
Markus
I opened my thread about my babysteps of my Class D Rookie... Well... had some drawback, because I fried my hard disc by a short circuit from my 2kVA PSU ==> USB scope ==> internal GND of notebook ==> hard disc ==> enclosure of hard disc ==> screw at hard disc cover ==> metal rack on which the notebook was standing (while I thought it would be floating well isolated...
) ==> PSU...OK, only the hard disc was fried, all the rest of the notebook seems to fine. ..running again.
I went on and since about one month I am strugling with the weaknesses of the IRS20954S. It is oversensitive vs noise. I managed to get it working up to something about 40A..50A even with the noise at hard switching conditions. But I wanted to have proper operation up to 60A..70A (did not work out so far) and then set the current limit to 55A. Furtheron the IC can be killed by the MosFets reverse capacity. I was able to cure this by an external driver.... STOP !!! Too many work arounds and still no satisfying behaviour. I think now I know why IR does promote this IC just for 200W, while the voltage rating and 1A driver capability in the data sheet would indicate to use it also in higher power amps...
I am right now changing my concept to:
Hysteresis resonator + level shift towards neg rail + IR2113 halfbridge driver + discrete shut down circuit
Will post the new schematic soon in my babystep thread.
Bye
Markus
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