Thank you Mr. Pass. The input impedance of a 100K to the trimmed DEF is the best and only value to adopt and use.
The pair of FEts understudy: SJDP120R085 [good device], and IRFP9140N were mounted on the large heat sink which I showed in post #103. The left picture shows their wiring scheme, and is described as follows:
1. I used a 2.5A fuse on each voltage rail of DEF.
2. A 0.5 Ohm resistor sensed the drain current of each FET
3. A 3300 uF bypass cap was connected at the drain of each FET.
4. The fan speed was set at its max level by using 115 Vac to drive it.
The experimental details are:
1. I used the procedures in posts #90 and #93 to characterize each FET individually. I used a 20 Ohm instead of the 25 Ohm load resistor which is shown in said posts. The purpose of this change was to enable DEF to reach its 1.3 A target idle bias. The power rating of this 20 Ohm resistor was ~20 W which was not adequate. So I mounted it in front of the air exit port of the heat sink to help it dissipate heat. It helped. This 20 Ohm load was not damaged. This is shown in the attached picture.
2. I also expanded the range of Vds from +/-5 V to +/-25 V by increasing its value using +/-5 V increments [c/o the variac of the PSU] This range included the target +/- 23 V at the idle of DEF.
3. The third picture shows the interface of the gates of the FETs on the heat sink with the protoboard on its rightside. Each gate was connected to its individual bias regulator which I had used in post #95.
The scanned document shows the numerical data I collected for each FET. The data of drain current [Id] were graphed versus its companion Vds while ensuring that the output offset voltage Vos ~0 Vdc. The relationship was pleasantly linear; maybe another charm of DEF. The Vgs values of each FET were recorded. The FETs' electrical characterisic [Id vs. Vds] were superimposable, suggesting a very good match between the two FETs.
The next step will be to connect the sources of the FETs [do without the 20 Ohm]; collect some data with focus on the stability of power dissipation.
1. I used a 2.5A fuse on each voltage rail of DEF.
2. A 0.5 Ohm resistor sensed the drain current of each FET
3. A 3300 uF bypass cap was connected at the drain of each FET.
4. The fan speed was set at its max level by using 115 Vac to drive it.
The experimental details are:
1. I used the procedures in posts #90 and #93 to characterize each FET individually. I used a 20 Ohm instead of the 25 Ohm load resistor which is shown in said posts. The purpose of this change was to enable DEF to reach its 1.3 A target idle bias. The power rating of this 20 Ohm resistor was ~20 W which was not adequate. So I mounted it in front of the air exit port of the heat sink to help it dissipate heat. It helped. This 20 Ohm load was not damaged. This is shown in the attached picture.
2. I also expanded the range of Vds from +/-5 V to +/-25 V by increasing its value using +/-5 V increments [c/o the variac of the PSU] This range included the target +/- 23 V at the idle of DEF.
3. The third picture shows the interface of the gates of the FETs on the heat sink with the protoboard on its rightside. Each gate was connected to its individual bias regulator which I had used in post #95.
The scanned document shows the numerical data I collected for each FET. The data of drain current [Id] were graphed versus its companion Vds while ensuring that the output offset voltage Vos ~0 Vdc. The relationship was pleasantly linear; maybe another charm of DEF. The Vgs values of each FET were recorded. The FETs' electrical characterisic [Id vs. Vds] were superimposable, suggesting a very good match between the two FETs.
The next step will be to connect the sources of the FETs [do without the 20 Ohm]; collect some data with focus on the stability of power dissipation.
Attachments
A DC-Coupled Prototype DEF amp
It sounds great through the 6 Ohm ADS L730 loudspeaker. Tight bass, sparkling highs, and clear-sung vocals. The amp's schematic is attached.
The amp has 3 supporting PSUs.
1. High power with rails spanning +/-5 to +/-25 V for DEF stage.
2. Regulated low power +/-12 V for OpAmps and support.
3. Unregulated and floating low power +/-27V. I show 5KuF filter caps in it. Each electrolytic is bypassed with 1 uF, 0.1 uF, 0.001uF polypropylene caps.
Note that the center tap of the power transformer inside this PSU is the signal output node.
Here's the amp's description starting on the left side of the schematic:
1. The constant current source [2N3819] generates a Vref = -0.66V across the 300 Ohm connected between the JFET's drain and ground.
2. This negative Vref is inverted by the OpAmp [LM356N] to generate a stable +0.66 V across its load of 165 Ohms. The resultant current flowing through this load is ~4 mA.
3. The OpAmp and associated support parts are a current source preamplifier for music signals and DC voltage. This DC voltage is the bias generator to each of the FETs in DEF.
4. The voltage supply rails of the OpAmp are cascoded by the indicated BJTs. Its voltage rails are now +/-11.4V.
5. The complementary cascoding BJTs operate in the common base configuration. Most the current flowing through their emitters emanates from the output stage BJTs inside the OpAmp. The output BJTs inside the OpAmp operate in the common emitter configuration. The supply current to the OpAmp is considered to be highly stable; which is highly desired for a stable biasing of the FETs in DEF
6. The DC and AC gain of the BJTs of the OpAmp's output stage is the ratio of the ~1K sum resistor at the center tap of the +/-27V PSU to 165 Ohm.
7. Thus the 4 mA flowing through the 165 Ohms flows through the ~1K load resistors and generates a -4 V to bias/tweak the Vgs of each FET in DEF.
Here's a procedure to bias the the DEF.
1. Adjust the voltage across the 1 K variable load resistor to -3.72V. This voltage is Vgs for P-MOS. Why -3.72 V? I already had established it from the previous characterization procedures of the power FETs.
2. Start at +/5 Vds by using the DEF variable PSU.
3. Null Vos [0 V] at the power output of DEF with the 50 Ohm variable load/bias resistor to R085.
4. Increase Vds in +/-5Vds increments and restore Vos to zero V with the 50 Ohm bias resistor to R085. As this FET's temperature increased, Vos drifted which required to manually zero it by increasing the value of the 50 Ohm variable resistor.
5. At +/-20Vds, drain current in FETs was roughly 1.1A, and Vos was <50 mV. Vos drifted a bit
6. The final and hot Vgs was ~-3.9 V and -3.72 V for R085 and P-MOS respectively; within the 0.3 V matching [their delta Vgs] quoted by Mr. Pass.
7. This amp was stable and ready for music.
It sounds great through the 6 Ohm ADS L730 loudspeaker. Tight bass, sparkling highs, and clear-sung vocals. The amp's schematic is attached.
The amp has 3 supporting PSUs.
1. High power with rails spanning +/-5 to +/-25 V for DEF stage.
2. Regulated low power +/-12 V for OpAmps and support.
3. Unregulated and floating low power +/-27V. I show 5KuF filter caps in it. Each electrolytic is bypassed with 1 uF, 0.1 uF, 0.001uF polypropylene caps.
Note that the center tap of the power transformer inside this PSU is the signal output node.
Here's the amp's description starting on the left side of the schematic:
1. The constant current source [2N3819] generates a Vref = -0.66V across the 300 Ohm connected between the JFET's drain and ground.
2. This negative Vref is inverted by the OpAmp [LM356N] to generate a stable +0.66 V across its load of 165 Ohms. The resultant current flowing through this load is ~4 mA.
3. The OpAmp and associated support parts are a current source preamplifier for music signals and DC voltage. This DC voltage is the bias generator to each of the FETs in DEF.
4. The voltage supply rails of the OpAmp are cascoded by the indicated BJTs. Its voltage rails are now +/-11.4V.
5. The complementary cascoding BJTs operate in the common base configuration. Most the current flowing through their emitters emanates from the output stage BJTs inside the OpAmp. The output BJTs inside the OpAmp operate in the common emitter configuration. The supply current to the OpAmp is considered to be highly stable; which is highly desired for a stable biasing of the FETs in DEF
6. The DC and AC gain of the BJTs of the OpAmp's output stage is the ratio of the ~1K sum resistor at the center tap of the +/-27V PSU to 165 Ohm.
7. Thus the 4 mA flowing through the 165 Ohms flows through the ~1K load resistors and generates a -4 V to bias/tweak the Vgs of each FET in DEF.
Here's a procedure to bias the the DEF.
1. Adjust the voltage across the 1 K variable load resistor to -3.72V. This voltage is Vgs for P-MOS. Why -3.72 V? I already had established it from the previous characterization procedures of the power FETs.
2. Start at +/5 Vds by using the DEF variable PSU.
3. Null Vos [0 V] at the power output of DEF with the 50 Ohm variable load/bias resistor to R085.
4. Increase Vds in +/-5Vds increments and restore Vos to zero V with the 50 Ohm bias resistor to R085. As this FET's temperature increased, Vos drifted which required to manually zero it by increasing the value of the 50 Ohm variable resistor.
5. At +/-20Vds, drain current in FETs was roughly 1.1A, and Vos was <50 mV. Vos drifted a bit
6. The final and hot Vgs was ~-3.9 V and -3.72 V for R085 and P-MOS respectively; within the 0.3 V matching [their delta Vgs] quoted by Mr. Pass.
7. This amp was stable and ready for music.
Attachments
Learning DEF
The attached schematic of DEF [less all of the numbers] was shown by Mr Pass at BAF 2016. The resistors: R2, R3 and R4 are the principal elements of his trimming technique. They establish an exact value of [hot] Vgs for each FET; so as to then give the following example amp idle conditions without an output load:
1. A stable drain current =1.3A flowing through each FET.
2. A +/- Vds = +/-23 V
3. A stable DC output offset [Vos] of 0V. Practically, a value of up to plus or minus 50 mV maybe allowed, so as to safely connect this output directly to a loudspeaker.
My DEF ~meets the above electrical conditions at the following Vgs measurements which are shown on the Pass schematic. They were established by using the DC coupled DEF amp [schematic] in my above post:
1. A stable hot Vgs = -3.72 V for IRFP9140N. This Vgs is established first, and is/becomes the baseline value to then trim Vgs of R085.
2. A stable hot Vgs = -4V to - 4.2V for my good R085. The exact value happens at a stable Vos ~0V; by adjusting/trimming the value of R3 without disturbing Vgs of P-MOS.
The above two points say:
1. Vgs of P-MOS is less negative than Vgs of R085
2. R085 likes to operate close to its pinch-off Vgs = -5V
The picture of the fan-driven heatsink shows that I moved R085 to be close to P-MOS. This allows for the best thermal tracking of the FETs. It also allows for a rapid heatup of R085 to a steady state hot temperature; so as to stabilize its Vgs. I used clamps to affix R085 to this type of surplus heatsink meant for mounting TO-3s.
The operation of DEF maybe likened to a rope tug of war/match. For balance and/or the stability of its quiescent operating point, the conduction of its FETs oppose each other.
The attached schematic of DEF [less all of the numbers] was shown by Mr Pass at BAF 2016. The resistors: R2, R3 and R4 are the principal elements of his trimming technique. They establish an exact value of [hot] Vgs for each FET; so as to then give the following example amp idle conditions without an output load:
1. A stable drain current =1.3A flowing through each FET.
2. A +/- Vds = +/-23 V
3. A stable DC output offset [Vos] of 0V. Practically, a value of up to plus or minus 50 mV maybe allowed, so as to safely connect this output directly to a loudspeaker.
My DEF ~meets the above electrical conditions at the following Vgs measurements which are shown on the Pass schematic. They were established by using the DC coupled DEF amp [schematic] in my above post:
1. A stable hot Vgs = -3.72 V for IRFP9140N. This Vgs is established first, and is/becomes the baseline value to then trim Vgs of R085.
2. A stable hot Vgs = -4V to - 4.2V for my good R085. The exact value happens at a stable Vos ~0V; by adjusting/trimming the value of R3 without disturbing Vgs of P-MOS.
The above two points say:
1. Vgs of P-MOS is less negative than Vgs of R085
2. R085 likes to operate close to its pinch-off Vgs = -5V
The picture of the fan-driven heatsink shows that I moved R085 to be close to P-MOS. This allows for the best thermal tracking of the FETs. It also allows for a rapid heatup of R085 to a steady state hot temperature; so as to stabilize its Vgs. I used clamps to affix R085 to this type of surplus heatsink meant for mounting TO-3s.
The operation of DEF maybe likened to a rope tug of war/match. For balance and/or the stability of its quiescent operating point, the conduction of its FETs oppose each other.
Attachments
Experimenting with DEF
All my experiments with DEF lead to the attached prize [simple/effective] schematic by Mr. Pass. The series connected resistors R2, R3 and R4 enable the following 3 functions:
1. Bias the FETs in DEF [generate Vgs for each] with the -12V power supply.
2. Enable a pathway to increase the input resistance of this amp via bootstrapping; by adopting the approach of Mr. Pass shown in an earlier post.
3. This third function is another testament to the genius of Mr. Pass. DEF automatically adjusts its output DC offset [Vos] to zero; meaning a simple and highly effective DC servo for direct coupling to a loudspeaker.
Here's the operation of this neat Pass Auto-Zeroing DEF:
1. Model the FETs as power resistors of equal value which are passing 1.3A at idle. The resultant DEF's Vos is equal to/centers at exactly zero Volts relative to ground.
2. Suppose Vos suddenly jumps to +50 mV. This says that the channel resistance of P-MOS increases slightly, and/or the channel resistance of R085 decreases slightly.
3. It follows that the resultant new current flowing throughthe R2, R3 and R4 bias ladder increases; because the value of the power supply across them resistors is now -12.05V.
4. It follows that the new value of Vgs for P-MOS becomes a bit more negative than -3.65V. This enhances the conduction of P-MOS which decreases its channel resistance; such that its new resistance multiplied by 1.3A restores Vos back to zero V.
5. It also follows due to the step jump of Vos from zero Volts to +50 mV, that the new [bias] voltage drop across [R2 and R3] also decreases or becomes a bit more negative than -3.97V. This new Vgs for R085 chokes its drain-source channel, and slightly increases its resistance; such that its new resistance multiplied by 1.3A restores Vos back to zero Volts.
6. The opposite electrical activity occurs when Vos suddenly drops to -50 mV.
The resistance values for R2, R3, and R4 are initially chosen/adjusted outside DEF to generate the shown values of Vgs. The values of the Vgs' had already been established in past experiments. These bias voltages are next offered to the FETs at zero +/-Vds. Power to DEF is next applied and +/-Vds is ramped up slowly in increments of +/-5 Vds, with measurements in between until a +/-Vds = 23V is reached.
The Vos of my DEF [at temperature and idle] fluctuated +/-150 mV; a bit loose. Maybe due to the -12V PSU, ripple on it..or something else; but it worked beautifully. I was able to augment the Pass Auto Zeroing DEF with an additional classical OpAmp-based DC servo without difficulty; if needed.
to be continued..
All my experiments with DEF lead to the attached prize [simple/effective] schematic by Mr. Pass. The series connected resistors R2, R3 and R4 enable the following 3 functions:
1. Bias the FETs in DEF [generate Vgs for each] with the -12V power supply.
2. Enable a pathway to increase the input resistance of this amp via bootstrapping; by adopting the approach of Mr. Pass shown in an earlier post.
3. This third function is another testament to the genius of Mr. Pass. DEF automatically adjusts its output DC offset [Vos] to zero; meaning a simple and highly effective DC servo for direct coupling to a loudspeaker.
Here's the operation of this neat Pass Auto-Zeroing DEF:
1. Model the FETs as power resistors of equal value which are passing 1.3A at idle. The resultant DEF's Vos is equal to/centers at exactly zero Volts relative to ground.
2. Suppose Vos suddenly jumps to +50 mV. This says that the channel resistance of P-MOS increases slightly, and/or the channel resistance of R085 decreases slightly.
3. It follows that the resultant new current flowing throughthe R2, R3 and R4 bias ladder increases; because the value of the power supply across them resistors is now -12.05V.
4. It follows that the new value of Vgs for P-MOS becomes a bit more negative than -3.65V. This enhances the conduction of P-MOS which decreases its channel resistance; such that its new resistance multiplied by 1.3A restores Vos back to zero V.
5. It also follows due to the step jump of Vos from zero Volts to +50 mV, that the new [bias] voltage drop across [R2 and R3] also decreases or becomes a bit more negative than -3.97V. This new Vgs for R085 chokes its drain-source channel, and slightly increases its resistance; such that its new resistance multiplied by 1.3A restores Vos back to zero Volts.
6. The opposite electrical activity occurs when Vos suddenly drops to -50 mV.
The resistance values for R2, R3, and R4 are initially chosen/adjusted outside DEF to generate the shown values of Vgs. The values of the Vgs' had already been established in past experiments. These bias voltages are next offered to the FETs at zero +/-Vds. Power to DEF is next applied and +/-Vds is ramped up slowly in increments of +/-5 Vds, with measurements in between until a +/-Vds = 23V is reached.
The Vos of my DEF [at temperature and idle] fluctuated +/-150 mV; a bit loose. Maybe due to the -12V PSU, ripple on it..or something else; but it worked beautifully. I was able to augment the Pass Auto Zeroing DEF with an additional classical OpAmp-based DC servo without difficulty; if needed.
to be continued..
Attachments
Experimenting with DEF
The stability of the DEF's idle current [~1.3A] was studied in order to identify the circuit component which manage it. The attached Pass Auto Zeroing DEF schematic shows the following:
1. I've implemented the bootstrap circuit suggested by Mr. Pass in an earlier post.
2. The resistor values were measured at the end of the experiment [after trimming], and out of circuit.
3. The values of Vgs for each FET were measured at the point when their drain current was rock stable [+/-1 mA].
4. Note the resistor which trims Vos. Easy to do and it put Vos in the stable range of +50 mV to -50 mV.
5. Note the fixed resistors [40 Ohm] and the variable potentiometer [25 Ohm]. The voltage drop across both of them stabilized idle current by predominantly minimizing the value of Vgs for R085.
One picture shows that I mounted the FETs next to each other so as to maximize the effect of temperature on the stability of idle current, and to thereafter manage it. Both FETs were clamped to the sink [using mica, and ZnO goop] and are shown under the lower clamp. Their center to center spacing was ~16 mm.
The second picture shows the variable resistors used for the trimming voltage ladder. The bottom pot is 500 Ohms and was adjusted to 365 Ohms. The two fixed resistors are 10 and 27 [measures 30 Ohms] = the fixed 40 Ohms shown in the schematic. The 25 Ohm pot fine-tuned Vgs of R085. Each of two 500 Ohm pots on the perforated board was adjusted to 387 Ohms. Their center joint received the bootstrap voltage.
On power up [+/-5 Vds increments; ~30 seconds] to get to +/-23 Vds. Idle current began at ~1.2A, and it steadily increased. The resistance of the 25 Ohm pot was increased when drain current exceeded 1.30A. This decreased Vgs of R085, and I lowered drain current to ~1.25A as the new starting point. Drain current was monitored across the sense resistors, and the aforementioned trim repeated until Id = 1.30 A at steady state.
I drove the resultant DEF with a 5X gain inverting OpAmp which I assembled on the adjacent protoboard. I limited the power output voltage of DEF to 4 Vp-p across a 4 Ohm shelf loudspeaker. It sounded great and highly detailed. No hum or hiss were detected by my ears. There was no indication of this noise on the scope.
The upcoming Part 2 is another heat stability experiment. Each FET in DEF will sit on its heatsink, and will not be coupled thermally.
The stability of the DEF's idle current [~1.3A] was studied in order to identify the circuit component
1. I've implemented the bootstrap circuit suggested by Mr. Pass in an earlier post.
2. The resistor values were measured at the end of the experiment [after trimming], and out of circuit.
3. The values of Vgs for each FET were measured at the point when their drain current was rock stable [+/-1 mA].
4. Note the resistor which trims Vos. Easy to do and it put Vos in the stable range of +50 mV to -50 mV.
5. Note the fixed resistors [40 Ohm] and the variable potentiometer [25 Ohm]. The voltage drop across both of them stabilized idle current by predominantly minimizing the value of Vgs for R085.
One picture shows that I mounted the FETs next to each other so as to maximize the effect of temperature on the stability of idle current, and to thereafter manage it. Both FETs were clamped to the sink [using mica, and ZnO goop] and are shown under the lower clamp. Their center to center spacing was ~16 mm.
The second picture shows the variable resistors used for the trimming voltage ladder. The bottom pot is 500 Ohms and was adjusted to 365 Ohms. The two fixed resistors are 10 and 27 [measures 30 Ohms] = the fixed 40 Ohms shown in the schematic. The 25 Ohm pot fine-tuned Vgs of R085. Each of two 500 Ohm pots on the perforated board was adjusted to 387 Ohms. Their center joint received the bootstrap voltage.
On power up [+/-5 Vds increments; ~30 seconds] to get to +/-23 Vds. Idle current began at ~1.2A, and it steadily increased. The resistance of the 25 Ohm pot was increased when drain current exceeded 1.30A. This decreased Vgs of R085, and I lowered drain current to ~1.25A as the new starting point. Drain current was monitored across the sense resistors, and the aforementioned trim repeated until Id = 1.30 A at steady state.
I drove the resultant DEF with a 5X gain inverting OpAmp which I assembled on the adjacent protoboard. I limited the power output voltage of DEF to 4 Vp-p across a 4 Ohm shelf loudspeaker. It sounded great and highly detailed. No hum or hiss were detected by my ears. There was no indication of this noise on the scope.
The upcoming Part 2 is another heat stability experiment. Each FET in DEF will sit on its heatsink, and will not be coupled thermally.
Attachments
Experimenting with DEF
This is the Part 2 experiment suggested in the previous post. The attached picture shows the two DEF FETs clamped securely onto separate heat sinks. The sinks were shorted electrically via a wire with 2 alligator clips, and then grounded. The bottom of the picture also shows an alcohol thermometer [yellow] which was inserted inside and between two fins of the R085 heat sink. After a long time idle [fan running], the max temp it measured was ~30 Celsius. The effluent air plus the metal sinks by touch were lukewarm.
The schematic attendant to this DEF is attached. Please note the following:
1. The numerical difference between the measured Vgs of the FETs was lower in value [~0.3V] than the [~0.5V] when both FETs were side by side on one heat sink. This [0.3V] value was observed in past experiments and is understood to mean [per Mr. Pass] that these two FETs are matched at steady state at the indicated conditions of the experiment.
2. The above point suggests mounting the FETs as far apart as allowed on a practical one piece heatsink. By example are the two power Mosfets in F7 [shown in reviews] which are well separated on one practical heasink.
3. The variable resistors and their specific purpose did not change; for offset control, and for the stabilty against the upward drift of the quiescent/idle drain current.
I observed DEF during the first minute after power turn on with cold heatsinks so as to assess potential problems. The ongoings were:
1. Turn power on to the auto-zeroing resistor ladder.
2. No load to DEF
3. Monitor drain current across one sense resistor as Vds is dialed up [via variac] to +/-23V in 10 seconds. The transient drain current did not exceed ~1A which was my principal concern.
4. At ~20 seconds, drain current was at ~1.1A, and the DC voltage at the power output was contained between +/100 mV.
5. Drain current drifted up to ~1.28 A, and thereafter it stayed put. Vds was fine-tuned to exactly +/-23 V.
6. Drain current was still stable after an additional one hour. The magnitude of DC offset was then tweaked using the pots in the schematic so as to contain it within +/-50 mV.
7. DEF was monitored for an extra hour with particular focus on the stability of drain current, and the stabilty of DC offset.
8. Power to DEF was turned off, and was followed 10 seconds later by turning power off to the auto zeroing resistor ladder.
The DEF amp was cycled several times between cold starts and idle lukewarm heatsinks as described above. Its behavior was reproducible. Minimum tweaks [via the variable pots, and Vds] were done during each cycle if/where needed.
This is the Part 2 experiment suggested in the previous post. The attached picture shows the two DEF FETs clamped securely onto separate heat sinks. The sinks were shorted electrically via a wire with 2 alligator clips, and then grounded. The bottom of the picture also shows an alcohol thermometer [yellow] which was inserted inside and between two fins of the R085 heat sink. After a long time idle [fan running], the max temp it measured was ~30 Celsius. The effluent air plus the metal sinks by touch were lukewarm.
The schematic attendant to this DEF is attached. Please note the following:
1. The numerical difference between the measured Vgs of the FETs was lower in value [~0.3V] than the [~0.5V] when both FETs were side by side on one heat sink. This [0.3V] value was observed in past experiments and is understood to mean [per Mr. Pass] that these two FETs are matched at steady state at the indicated conditions of the experiment.
2. The above point suggests mounting the FETs as far apart as allowed on a practical one piece heatsink. By example are the two power Mosfets in F7 [shown in reviews] which are well separated on one practical heasink.
3. The variable resistors and their specific purpose did not change; for offset control, and for the stabilty against the upward drift of the quiescent/idle drain current.
I observed DEF during the first minute after power turn on with cold heatsinks so as to assess potential problems. The ongoings were:
1. Turn power on to the auto-zeroing resistor ladder.
2. No load to DEF
3. Monitor drain current across one sense resistor as Vds is dialed up [via variac] to +/-23V in 10 seconds. The transient drain current did not exceed ~1A which was my principal concern.
4. At ~20 seconds, drain current was at ~1.1A, and the DC voltage at the power output was contained between +/100 mV.
5. Drain current drifted up to ~1.28 A, and thereafter it stayed put. Vds was fine-tuned to exactly +/-23 V.
6. Drain current was still stable after an additional one hour. The magnitude of DC offset was then tweaked using the pots in the schematic so as to contain it within +/-50 mV.
7. DEF was monitored for an extra hour with particular focus on the stability of drain current, and the stabilty of DC offset.
8. Power to DEF was turned off, and was followed 10 seconds later by turning power off to the auto zeroing resistor ladder.
The DEF amp was cycled several times between cold starts and idle lukewarm heatsinks as described above. Its behavior was reproducible. Minimum tweaks [via the variable pots, and Vds] were done during each cycle if/where needed.
Attachments
Experimenting with DEF
A DEF amp is easy to assemble, and to trim so as to give it a stable quiescent drain current, plus a minimum output DC offset for direct coupling to a loudspeaker. DEF amp is expected to have only one +/-23V power supply per the simple design approach of Mr. Pass. The attached schematic is practical, and is for the recent prototype understudy: The principal focus is on the resistor ladder which generates the required stable Vgs for each FET in DEF. I hope that it is understood that the two FETs and the resistor ladder collectively render this assembly auto zeroing. Please note the following:
1. The resistor ladder is sandwiched between Vout [at 0 Vdc], and -23.3V. I am using a separate power supply for -23.3V; but this power supply will be eliminated in favor of using the negative voltage rail of DEF.
2. The ripple at the drains of the FETs, and the need for a ripple filter/capacitor [220 uF] at the bottom of the ladder. This allows DEF to only correct for Vout offsets, and not be bothered with ripple if present.
3. The bootstrap capacitor [220 uF] which will raise the load resistance to the preamp driving at Vin. I show a 220 uF at Vin and also for bootstrap which are overkill [I have'm]. Both caps will be lower in value and hopefully be of high quality for sonics.
4. The sum of R3 and R4 or actually the sum voltage drop across them is very important for the magnitude of the desired quiescent drain current [1.3A] and for its stability against upward drift. This measured voltage drop in my DEF [0.57V] is lower than the value of Vgs for P-MOS [-3.73V] which is needed to generate the optimum Vgs for R085. This difference [0.57V] in the Vgs values between P-MOS and R085 is uniquely characteristic to this pair of FETs understudy. No other values; meaning higher or lower than this difference gave me a stable 1.3A drain current at a Vds of +/-23.3V.
5. My pair of FETs are thus matched to exactly 0.57 V.
6. The relevant FET to bias properly is mostly R085. Most of the trimming suggested by Mr. Pass happened at R3+R4; with the R4 variable pot.
I thank Mr. Pass for his generosity. He gave me two R085s. I'll use them to continue my studies; like to initially compare them with my old faithfull R085.
A DEF amp is easy to assemble, and to trim so as to give it a stable quiescent drain current, plus a minimum output DC offset for direct coupling to a loudspeaker. DEF amp is expected to have only one +/-23V power supply per the simple design approach of Mr. Pass. The attached schematic is practical, and is for the recent prototype understudy: The principal focus is on the resistor ladder which generates the required stable Vgs for each FET in DEF. I hope that it is understood that the two FETs and the resistor ladder collectively render this assembly auto zeroing. Please note the following:
1. The resistor ladder is sandwiched between Vout [at 0 Vdc], and -23.3V. I am using a separate power supply for -23.3V; but this power supply will be eliminated in favor of using the negative voltage rail of DEF.
2. The ripple at the drains of the FETs, and the need for a ripple filter/capacitor [220 uF] at the bottom of the ladder. This allows DEF to only correct for Vout offsets, and not be bothered with ripple if present.
3. The bootstrap capacitor [220 uF] which will raise the load resistance to the preamp driving at Vin. I show a 220 uF at Vin and also for bootstrap which are overkill [I have'm]. Both caps will be lower in value and hopefully be of high quality for sonics.
4. The sum of R3 and R4 or actually the sum voltage drop across them is very important for the magnitude of the desired quiescent drain current [1.3A] and for its stability against upward drift. This measured voltage drop in my DEF [0.57V] is lower than the value of Vgs for P-MOS [-3.73V] which is needed to generate the optimum Vgs for R085. This difference [0.57V] in the Vgs values between P-MOS and R085 is uniquely characteristic to this pair of FETs understudy. No other values; meaning higher or lower than this difference gave me a stable 1.3A drain current at a Vds of +/-23.3V.
5. My pair of FETs are thus matched to exactly 0.57 V.
6. The relevant FET to bias properly is mostly R085. Most of the trimming suggested by Mr. Pass happened at R3+R4; with the R4 variable pot.
I thank Mr. Pass for his generosity. He gave me two R085s. I'll use them to continue my studies; like to initially compare them with my old faithfull R085.
Attachments
Experimenting with DEF
The schematic of the DEF understudy shows the joined gates of its FETs to be ~4Vdc below common/ground. This bias voltage is essentially "subtracted" from the gate-drain voltage of P-Mosfet. The "lost" 4 Vdc was restored by using an asymmetric PSU of [+23V] for R085 and [-28V] for IRFP9140 P-Mosfet.
The revised PSU is shown in the attached schematic. A low voltage unregulated PSU [~5 Vdc/~3A] was put in series with the negative rail [-23 V] of the parent +/-23V PSU to get to a -28 Vdc power rail.
No problems were encountered upon the slow PSU startup [via variac] or at shutdown. This DEF was cycled cold/hot twice. It was stable against the upward drift of its 1.3A drain current.
The resultant DEF sounded great driving a 6 Ohm full range loudspeaker. The revised PSU is expected to increase its power output by allowing added headroom to the input/output music signals.
The schematic of the DEF understudy shows the joined gates of its FETs to be ~4Vdc below common/ground. This bias voltage is essentially "subtracted" from the gate-drain voltage of P-Mosfet. The "lost" 4 Vdc was restored by using an asymmetric PSU of [+23V] for R085 and [-28V] for IRFP9140 P-Mosfet.
The revised PSU is shown in the attached schematic. A low voltage unregulated PSU [~5 Vdc/~3A] was put in series with the negative rail [-23 V] of the parent +/-23V PSU to get to a -28 Vdc power rail.
No problems were encountered upon the slow PSU startup [via variac] or at shutdown. This DEF was cycled cold/hot twice. It was stable against the upward drift of its 1.3A drain current.
The resultant DEF sounded great driving a 6 Ohm full range loudspeaker. The revised PSU is expected to increase its power output by allowing added headroom to the input/output music signals.
Attachments
Experimenting with DEF
I used three 2SJDP120R085s and one UJN1208K in the "standard" DEF circuit understudy. The aforementioned four FETs were mated with the same IRFP9140 P-Mosfet for consistency. Please take a look at the attached picture for results. The resistor ladder which biased DEF in my past posts was used to extricate the important Vgs for each depletion FET.
1. The FETs were affixed to separate heatsinks.
2. The quiescent conditions for each resulting DEF were the same at 1.3A drain currents and +/-23V Vds.
3. Note the legend or identity of the depletion FETs on the left of the view.
4. The values of Vgs which have the "boldest" font are the important results.
5. The current of 1.130 mA was kept ~constant inside each resistor ladder so as to develop a reference Vgs =-3.73V for IRFP9140.
6. The two resistors of most/mighty importance in each resistor ladder are sandwiched between the Vgs of NJF and the Vgs=-3.73V of IRFP9140.
The following conclusions emerged:
1. The values of Vgs for the three R085s are in a broad distribution [bell curve] of many such results. This is normal in the production of anything including semiconductor devices. This DEF circuit understudy will readily measure the many Vgs values of R085 embedded in its production's distribution.
2. UJN1208K behaved as well as R085. This expanded the utility of DEF.
3. By far, this is the most important conclusion and advice from this study. Use the resistor ladder for R085 identified as Pass #16. He also gave me Pass #7 which is a close match to #16. I did not know the value of Vgs for UJN1208K in DEF. So I maximized the value of the two resistors [R6 and R7] in Pass #16 which are sandwiched between Vgs of R085 and Vgs=-3.73V of P-Mos. This protected NJF from absurdly damaging high currents [>2A measured ] at even a low Vds of 0.2V. So I started at a very low Vgs which was at or even lower than its pinchoff value. Next, the Vgs of NJF was slowly increased by decreasing the value of the sandwiched resistors [R6 and R7], and simultaneously and equally increasing the value of any of the other resistors in the ladder; but not 3.3K so as pass in the chain a resultant constant 1.130 mA.
Mr. Pass talked about using IRFP9240 with R085 in DEF at BAF 2016. Fortunately, it has the same spec Vgs value -2 to -4V like IRFP9140 which I am using. Thus, a practical Vgs =-3.73V maybe a great starting value for IRFP9240 in your studies/build of DEF.
I used three 2SJDP120R085s and one UJN1208K in the "standard" DEF circuit understudy. The aforementioned four FETs were mated with the same IRFP9140 P-Mosfet for consistency. Please take a look at the attached picture for results. The resistor ladder which biased DEF in my past posts was used to extricate the important Vgs for each depletion FET.
1. The FETs were affixed to separate heatsinks.
2. The quiescent conditions for each resulting DEF were the same at 1.3A drain currents and +/-23V Vds.
3. Note the legend or identity of the depletion FETs on the left of the view.
4. The values of Vgs which have the "boldest" font are the important results.
5. The current of 1.130 mA was kept ~constant inside each resistor ladder so as to develop a reference Vgs =-3.73V for IRFP9140.
6. The two resistors of most/mighty importance in each resistor ladder are sandwiched between the Vgs of NJF and the Vgs=-3.73V of IRFP9140.
The following conclusions emerged:
1. The values of Vgs for the three R085s are in a broad distribution [bell curve] of many such results. This is normal in the production of anything including semiconductor devices. This DEF circuit understudy will readily measure the many Vgs values of R085 embedded in its production's distribution.
2. UJN1208K behaved as well as R085. This expanded the utility of DEF.
3. By far, this is the most important conclusion and advice from this study. Use the resistor ladder for R085 identified as Pass #16. He also gave me Pass #7 which is a close match to #16. I did not know the value of Vgs for UJN1208K in DEF. So I maximized the value of the two resistors [R6 and R7] in Pass #16 which are sandwiched between Vgs of R085 and Vgs=-3.73V of P-Mos. This protected NJF from absurdly damaging high currents [>2A measured ] at even a low Vds of 0.2V. So I started at a very low Vgs which was at or even lower than its pinchoff value. Next, the Vgs of NJF was slowly increased by decreasing the value of the sandwiched resistors [R6 and R7], and simultaneously and equally increasing the value of any of the other resistors in the ladder; but not 3.3K so as pass in the chain a resultant constant 1.130 mA.
Mr. Pass talked about using IRFP9240 with R085 in DEF at BAF 2016. Fortunately, it has the same spec Vgs value -2 to -4V like IRFP9140 which I am using. Thus, a practical Vgs =-3.73V maybe a great starting value for IRFP9240 in your studies/build of DEF.
Attachments
Experimenting with DEF.
The attached schematic shows a DEF which includes modifications to that I've been experimenting with. Please note the following:
1. A constant current source [CCS] enables a ~1.12 mA to flow through the resistor ladder which biases the FETs' drain currents to a stable 1.3A at a Vds = +/-23V. The value of this current [1.12 mA] had already been established as shown in an earlier post by using resistors.
2. Why the complexity of a CCS? Firstly, because of its high impedance which is the load to the preamp driving DEF, and thus the resultant prospect of using low valued film-type coupling caps for music signal purity . Secondly, this current [1.12mA] stays constant for a 28Vp-p music signal. The resultant Vgs values of the FETs are held constant. I'll show its schematic in a later post.
3. Two series-connected 15uF capacitors [C1 and C2; Ta] bridge the gates of the FETs. The music signal is symmetrically injected at their center series joint.
4. A third capacitor [C3=15uF] is connected between Vout and the center of the two resistors [of similar value] bridging the gates of the FETs.
5. This third capacitor can also be connected between Vout and Vin.
6. Why C3? It enables error correction in Vout on the proviso that a low impedance voltage source outputs/generates Vin.
Here's the relevance of C3 for error reduction. In an ideal world Vin and Vout [in a resistor load] are identical in value and phase. Thus, C3 is essentially a high impedance at any audio frequency. But; Vout contains harmonics generated by the FETs. The capacitor [C3] now shunts these add on harmonic signals to the to the Low Z output of the voltage source generating Vin. Good or bad for musicality, THD is expected to be lower than that shown in the graph by Mr. Pass at BAF 2016 for THD versus output power for DEF.
Back EMF is an additional add-on signal at Vout when DEF drives a loudspeaker. Any remnant is thus routed to the output of the low Z voltage source generating Vin. If this EMF happens at 30 Hz by example, the impedance of C3 is 350 Ohms. There's an upper limit to the value of C3. Thus C3 may provide a mechanism to increase the damping factor of DEF.
The attached schematic shows a DEF which includes modifications to that I've been experimenting with. Please note the following:
1. A constant current source [CCS] enables a ~1.12 mA to flow through the resistor ladder which biases the FETs' drain currents to a stable 1.3A at a Vds = +/-23V. The value of this current [1.12 mA] had already been established as shown in an earlier post by using resistors.
2. Why the complexity of a CCS? Firstly, because of its high impedance which is the load to the preamp driving DEF, and thus the resultant prospect of using low valued film-type coupling caps for music signal purity . Secondly, this current [1.12mA] stays constant for a 28Vp-p music signal. The resultant Vgs values of the FETs are held constant. I'll show its schematic in a later post.
3. Two series-connected 15uF capacitors [C1 and C2; Ta] bridge the gates of the FETs. The music signal is symmetrically injected at their center series joint.
4. A third capacitor [C3=15uF] is connected between Vout and the center of the two resistors [of similar value] bridging the gates of the FETs.
5. This third capacitor can also be connected between Vout and Vin.
6. Why C3? It enables error correction in Vout on the proviso that a low impedance voltage source outputs/generates Vin.
Here's the relevance of C3 for error reduction. In an ideal world Vin and Vout [in a resistor load] are identical in value and phase. Thus, C3 is essentially a high impedance at any audio frequency. But; Vout contains harmonics generated by the FETs. The capacitor [C3] now shunts these add on harmonic signals to the to the Low Z output of the voltage source generating Vin. Good or bad for musicality, THD is expected to be lower than that shown in the graph by Mr. Pass at BAF 2016 for THD versus output power for DEF.
Back EMF is an additional add-on signal at Vout when DEF drives a loudspeaker. Any remnant is thus routed to the output of the low Z voltage source generating Vin. If this EMF happens at 30 Hz by example, the impedance of C3 is 350 Ohms. There's an upper limit to the value of C3. Thus C3 may provide a mechanism to increase the damping factor of DEF.
Attachments
Experimenting with DEF
The attached schematic is for the prototype Integrated DEF Power Amp under study. Please note the following:
1. The constant current source [CCS; ~1.12 mA] at the upper left of the view. It was important to maximize the value of the fixed resistors in-line with the JFET's source [11.2K] so as to minimize the value of the control pot [100 Ohm] for the fine tweaking of the DC voltage offset at the output. The NPN cascode added stability to the JFET's constant current, and also protected the JFET from large voltage excursions of the music signal.
2. The Op Amp inverting line amplifier at the bottom left of the view. It summed the L and R headphone outputs of the CD player. It has a low output impedance. Some may consider using a Pass diy discrete OpAmp instead of LF356N.
3. The DC servo amplifier at the upper right of the view. The integrating capacitor is 1 uF metallized polypropylene. Its output control current flows through a 1 Meg resistor to the indicated destination. The voltage drop across this 1 Meg resistor is 0.7 Volts; meaning a 0.7 uA control current was added to or subtracted from 1.12 mA CC, so as to establish a stable +/-2 mV DC offset at the power output. The prototype under study was susceptible to the drift of its output DC offset; most probably due to variation in the temperature of the FETs [on separate heatsinks], and the loose layout of the components on the protoboard.
4. The load resistance at the output of the line amp is the parallel combination of 1 Meg from the DC servo, and the impedance of CCS. The value of the 1 Meg can be increased to higher values; say to 2.2 Meg because of the low value of the correction current [0.7 uA] from the DC servo. The resultant high input impedance will thus minimize the value of the capacitors bridging the gates of the FETs, and thus allow the use of metallized polypropylenes caps so as to preserve the integrity of the incoming music signal.
5. The switch at Vout. It connected Vout via the 220uF electrolytic capacitor to the center tap of the two resistors bridging the gates of the FETs. The previous post showed the value of the cap to be 15uF instead of 220uF. The new value of this cap can be further increased to 440uF or two paralleled 220uF caps. The potential impact of this cap on objective and subjective performance was discussed in the previous post. The sound of music with and without this cap as the sole variable was subjectively different.
The attached schematic is for the prototype Integrated DEF Power Amp under study. Please note the following:
1. The constant current source [CCS; ~1.12 mA] at the upper left of the view. It was important to maximize the value of the fixed resistors in-line with the JFET's source [11.2K] so as to minimize the value of the control pot [100 Ohm] for the fine tweaking of the DC voltage offset at the output. The NPN cascode added stability to the JFET's constant current, and also protected the JFET from large voltage excursions of the music signal.
2. The Op Amp inverting line amplifier at the bottom left of the view. It summed the L and R headphone outputs of the CD player. It has a low output impedance. Some may consider using a Pass diy discrete OpAmp instead of LF356N.
3. The DC servo amplifier at the upper right of the view. The integrating capacitor is 1 uF metallized polypropylene. Its output control current flows through a 1 Meg resistor to the indicated destination. The voltage drop across this 1 Meg resistor is 0.7 Volts; meaning a 0.7 uA control current was added to or subtracted from 1.12 mA CC, so as to establish a stable +/-2 mV DC offset at the power output. The prototype under study was susceptible to the drift of its output DC offset; most probably due to variation in the temperature of the FETs [on separate heatsinks], and the loose layout of the components on the protoboard.
4. The load resistance at the output of the line amp is the parallel combination of 1 Meg from the DC servo, and the impedance of CCS. The value of the 1 Meg can be increased to higher values; say to 2.2 Meg because of the low value of the correction current [0.7 uA] from the DC servo. The resultant high input impedance will thus minimize the value of the capacitors bridging the gates of the FETs, and thus allow the use of metallized polypropylenes caps so as to preserve the integrity of the incoming music signal.
5. The switch at Vout. It connected Vout via the 220uF electrolytic capacitor to the center tap of the two resistors bridging the gates of the FETs. The previous post showed the value of the cap to be 15uF instead of 220uF. The new value of this cap can be further increased to 440uF or two paralleled 220uF caps. The potential impact of this cap on objective and subjective performance was discussed in the previous post. The sound of music with and without this cap as the sole variable was subjectively different.
Attachments
Experimenting with DEF
Mr. Pass showed a graph of THD versus output power [into 8 Ohms] at BAF 2016. THD for the "first watt" was an impressive 0.01%. Thereafter it increased smoothly to [0.1% or 1%; couldn't tell] at 20W. The prototype DEF under study may or not perform like his. So, I planted my prototype DEF in a circuit which utilized overall negative feedback [ONF]. The schematic is attached. Please note the following:
1. DEF is in the feedback loop of the OpAmp [LF356N].
2. The output of LF356N drives the center point of the two series-connected resistors which bridge the gates of the FETs.
3. The power output node of DEF is returned to the inverting port of LF356N via a 15K feedback resistor.
4. The voltage drop across the sense resistor [150 Ohms] at the output of LF353N was 0V at idle. This meant that the string of series resistors spanning Vout and -23V was the sole contributor of the ~1.12 mA which generated the requisite Vgs for each FET.
5. The DC offset [Vos] at Vout was ~5 mV. Thus a DC servo is not needed.
The pros of ONF in this circuit were:
1. No capacitors are in the circuit. This integrated amp is DC coupled throughout.
2. An expected low and flat THD versus output power.
3. The output impedance is expected to be lower in magnitude than without ONF.
The cons of ONF were.
1. The "signature" sound of my DEF without ONF became the classical sound of an amp with ONF. A consequence of pro#3 above. The two sounds were different. Each sound is fully enjoyable and musical.
2. Added complexity of LF356N.
Mr. Pass showed a graph of THD versus output power [into 8 Ohms] at BAF 2016. THD for the "first watt" was an impressive 0.01%. Thereafter it increased smoothly to [0.1% or 1%; couldn't tell] at 20W. The prototype DEF under study may or not perform like his. So, I planted my prototype DEF in a circuit which utilized overall negative feedback [ONF]. The schematic is attached. Please note the following:
1. DEF is in the feedback loop of the OpAmp [LF356N].
2. The output of LF356N drives the center point of the two series-connected resistors which bridge the gates of the FETs.
3. The power output node of DEF is returned to the inverting port of LF356N via a 15K feedback resistor.
4. The voltage drop across the sense resistor [150 Ohms] at the output of LF353N was 0V at idle. This meant that the string of series resistors spanning Vout and -23V was the sole contributor of the ~1.12 mA which generated the requisite Vgs for each FET.
5. The DC offset [Vos] at Vout was ~5 mV. Thus a DC servo is not needed.
The pros of ONF in this circuit were:
1. No capacitors are in the circuit. This integrated amp is DC coupled throughout.
2. An expected low and flat THD versus output power.
3. The output impedance is expected to be lower in magnitude than without ONF.
The cons of ONF were.
1. The "signature" sound of my DEF without ONF became the classical sound of an amp with ONF. A consequence of pro#3 above. The two sounds were different. Each sound is fully enjoyable and musical.
2. Added complexity of LF356N.
