I'll read up on the shmitt-triggers, but right now i'm deep into VCXO's and phase-detectors.. (very interresting actually 
)complex stuff but shouldn't have to be all that complex either.. at least not when buying a complete VCXO from the start so one don't have to build it from crystal.. 
LPF might be the trickyest part, and I guess it will benefit from SMD.. You know where to find specs for Guido's VCXO's? (nothing on his pages that I could see)
)complex stuff but shouldn't have to be all that complex either.. at least not when buying a complete VCXO from the start so one don't have to build it from crystal.. LPF might be the trickyest part, and I guess it will benefit from SMD.. You know where to find specs for Guido's VCXO's? (nothing on his pages that I could see)
Uh, hate to tell you.............phase detectors, VCXOs.......put them together equals PLL. Yes, that is complex. Do not attempt to make your own. The LPF is tricky, because you need to design what we call a Type 2 system. Has nothing to do with the order of the LPF, which by coincidence is second order. You need to know the phase detector gain, the VCXO gain, and come up with a settling time and damping factor that will allow it to work without pumping, overshoot, undershoot, and other instability problems. Not something a newbie should even dream of making.
Yes, I have made my own, to make phase noise measurements. But I have been doing this for over 30 years. (OK, I started making them in university, but I had years of making other ham radio stuff. My first one didn't work, but it was probably due to a silly oversight in the counter logic.............don't ask.)
Specs for Guido's VCXOs?.........I believe that he tells you all that a DIYer would need to know. If he doesn't tell you, then it probably won't do you a lick of good to know.
Jocko
Yes, I have made my own, to make phase noise measurements. But I have been doing this for over 30 years. (OK, I started making them in university, but I had years of making other ham radio stuff. My first one didn't work, but it was probably due to a silly oversight in the counter logic.............don't ask.)
Specs for Guido's VCXOs?.........I believe that he tells you all that a DIYer would need to know. If he doesn't tell you, then it probably won't do you a lick of good to know.
Jocko
Hey, What if I just copy Mark Heijligers VCXO circuit (http://httpd.chello.nl/~m.heijligers/DAChtml/dig_r2c.pdf), I can even copy (roughly) the PCB layout of the VCXO circuit.. Uses a Raltron VC7225 VCXO.. ??
Folks, I realize the LPF of a VCXO circuit is **** to design, but I'm just thinking a little on the subject... The VCXO itself is voltage controlled as the name suggests, right? So supplying the control pin with a constant voltage would render the VCXO functioning basically as a regular XO?
But what if I build my flipflop/NAND-based phase detector, and (with logics or a simple MCU) uses a digital potentiometer to control the voltage setting of a TL431 shunt regulator, wich in turns supplies the control pin of the VCXO? A stupid idea? Tell me why this is not going to work...
But what if I build my flipflop/NAND-based phase detector, and (with logics or a simple MCU) uses a digital potentiometer to control the voltage setting of a TL431 shunt regulator, wich in turns supplies the control pin of the VCXO? A stupid idea? Tell me why this is not going to work...
MAX5451 dual 10Kohm digital pots provide 256 steps with "manual" increment/decrement (no MCU needed if the logics is feasible).. If the two channels are paralelled, the chip could provide 0ohms to 5Kohms with 65536 steps, but I would have to come up with some logic system that sets a flag so that the logics "knows" wich channel to increment/decrement next...
Assuming I intime will get a sync clock (VCXO) for the DAC one way or the other, it will need FSYNC to syncronize, and pickup incoming clock on the line marked "RECLOCK" in the schematic, right? displayed is the interface I2S->DAC, the I2S line runs straight from the CS8412 reciever chip. Any obvious wrongs?
Attachments
I've designed plenty of PLL's in my lifetime... here's a bit of good info:
Make sure you get a chip which has a current output, not a voltage output, it makes the math a lot easier and prevents frequency-dependent phenomena from happening. The chips I almost always use are the National LMX2306 and the Analog Devices ADF4116. The latter is a superior clone of the former. They come in TSSOP packages so I hope you like surface mount design - but building a through-hole PLL is almost always asking for trouble. Been there, done that.
Next, select a VCXO. If you're generating a common audio clock, you can probably get a part from a Digikey or Allied catalog. E-mail the manufacturer and find out what the input *resistance* (not impedance) of their PLL is. If there's an input resistor to ground, then you'll either have to modify your passive loop filter design to include it or you'll have to use an active filter.
First of all get "Dean's Book" from national.com. Read this book through and through until you understand how a PLL works. Here's the URL:
http://www.national.com/appinfo/wireless/files/Deansbook3.pdf
Chances are you're going to design a 3rd order, passive loop filter if you're feeding a VCXO. The math is relatively easy for those. If you have access to MATLAB or even QuickBASIC, then write some programs to calculate component values from phase margin, natural frequency, pole ratio, etc. Try to keep the value of your resistors to 10K, and the value of your capacitors greater than 100pf but still within the range of available NPO and X5R surface mount ceramics. Don't use any exotic oil/paper/etc capacitors.
If you can't get good values for the system you're trying to design, then try moving to an active loop filter. There's a few good advantages here - you can easily make a loop filter with gain or attenuation, which can make component value selection a lot nicer. You can also feed VCXOs that have input resistances, if you're stuck with one.
Once you've got components you're happy with, use WEBENCH on national.com's website to plot some curves for your PLL. Also download Analog Devices' SIMPLL software and run the same tests there.
When you build it, here's the rules...
- your board must have a ground plane.
- decouple the hell out of your VCXO and PLL chips.
- If you have a clean 12 or 15V avalable, then use a 78L05 or similar regulator to regulate a charge pump voltage for your PLL chip, but don't skimp on the capacitance after the regulator.
- First capacitor of the loop filter goes directly in front of the output/ground pins of the PLL chip. Last capacitor of the loop filter goes directly across the input/ground pins of the VCXO.
Hope this helps a little. If you come up with something, i'll gladly comment on it.
Make sure you get a chip which has a current output, not a voltage output, it makes the math a lot easier and prevents frequency-dependent phenomena from happening. The chips I almost always use are the National LMX2306 and the Analog Devices ADF4116. The latter is a superior clone of the former. They come in TSSOP packages so I hope you like surface mount design - but building a through-hole PLL is almost always asking for trouble. Been there, done that.
Next, select a VCXO. If you're generating a common audio clock, you can probably get a part from a Digikey or Allied catalog. E-mail the manufacturer and find out what the input *resistance* (not impedance) of their PLL is. If there's an input resistor to ground, then you'll either have to modify your passive loop filter design to include it or you'll have to use an active filter.
First of all get "Dean's Book" from national.com. Read this book through and through until you understand how a PLL works. Here's the URL:
http://www.national.com/appinfo/wireless/files/Deansbook3.pdf
Chances are you're going to design a 3rd order, passive loop filter if you're feeding a VCXO. The math is relatively easy for those. If you have access to MATLAB or even QuickBASIC, then write some programs to calculate component values from phase margin, natural frequency, pole ratio, etc. Try to keep the value of your resistors to 10K, and the value of your capacitors greater than 100pf but still within the range of available NPO and X5R surface mount ceramics. Don't use any exotic oil/paper/etc capacitors.
If you can't get good values for the system you're trying to design, then try moving to an active loop filter. There's a few good advantages here - you can easily make a loop filter with gain or attenuation, which can make component value selection a lot nicer. You can also feed VCXOs that have input resistances, if you're stuck with one.
Once you've got components you're happy with, use WEBENCH on national.com's website to plot some curves for your PLL. Also download Analog Devices' SIMPLL software and run the same tests there.
When you build it, here's the rules...
- your board must have a ground plane.
- decouple the hell out of your VCXO and PLL chips.
- If you have a clean 12 or 15V avalable, then use a 78L05 or similar regulator to regulate a charge pump voltage for your PLL chip, but don't skimp on the capacitance after the regulator.
- First capacitor of the loop filter goes directly in front of the output/ground pins of the PLL chip. Last capacitor of the loop filter goes directly across the input/ground pins of the VCXO.
Hope this helps a little. If you come up with something, i'll gladly comment on it.
It will work. My only worry is metastability - make sure that whenever RECLOCK goes high, the SCK/FSYNC/DATA lines are *not* transitioning.cathode_leak said:
I'd use SCK instead of FSYNC to drive the PLL; it lets you run a higher phase detector frequency without running into any clock phase ambiguity. Your PLL should be 1:1, and it will give you a new SCLK, which I'll call nSCK.
Don't resample the incoming SCK; throw it out.
I2S samples data/frame sync on the rising edge, which is what you're getting from nSCK. So use nSCK to drive your (rising-edge triggered) flip-flops. Now since you've introduced a half-clock delay by resampling, use an inverter to invert nSCK - this is your new SCK for your DAC.
You can use two flip-flops; drive the first flip-flop and your DAC with nSCK, and drive the second flip-flip with /nSCK. But it's not really needed. Just make sure that your retimed nSCK signal has a close enough phase to the original SCK.cathode_leak said:Thanks very much for your replies GM. I'll get rid of the SCK and replace it with the clean one
If the CS8412 is putting out a stable SCK and your PLL is locked, then the recovered nSCK should be in phase, so sampling FS/data on the rising edge of nSCK should be fine. In reality there will be a bit of phase lag on nSCK and there will be a bit of phase jitter on SCK, but it shouldn't be any more than a few degrees. So everything should work OK.
If the CS8412's PLL is unlocked or your PLL is unlocked, then the SCK and nSCK signals won't be aligned. When this happens, god knows what sound your DAC will put out. It might be worth taking the unlock signals from the 8412 and PLL, and using them to mute/unmute the DACs you're using if there's no SPDIF signal.
Thanx GM
I have not yet decided wether I'm going to attempt an VCXO circuit myself, but I am concidering it. SMT design isn't exactly my alley, but I realize there are no good reason for not surface-mounting a VCXO circuit. I have friends very capable of SMT mounting, so I'll let others take care of the difficult soldering..
Say I'll take your advice and goes for the ADF4116 PLL... Could you advice a good low-jitter VCXO to go with it, that does not have an internal ground resistor? 'cause I would really like to avoid any digital filter...
I have not yet decided wether I'm going to attempt an VCXO circuit myself, but I am concidering it. SMT design isn't exactly my alley, but I realize there are no good reason for not surface-mounting a VCXO circuit. I have friends very capable of SMT mounting, so I'll let others take care of the difficult soldering..
Say I'll take your advice and goes for the ADF4116 PLL... Could you advice a good low-jitter VCXO to go with it, that does not have an internal ground resistor? 'cause I would really like to avoid any digital filter...
This one goes to Jocko, regarding the SPDIF input..
Would it be a solution if I use a buffered inverter like a VHC04, followed by a resistor to gnd (on both signals) before entering the CS8412 inputs? I might be way off here, but I'm thinking that the energy from the schmitt-trigger could be sent via the resistors to ground....?
Edit: added a schematic...
I am thinking that if Ra>Rb, the energy will have to follow Rb...
Re-edit: I don't need the inverter buffered if Ra>Rb... do I?
Jocko Homo said:
Would it be a solution if I use a buffered inverter like a VHC04, followed by a resistor to gnd (on both signals) before entering the CS8412 inputs? I might be way off here, but I'm thinking that the energy from the schmitt-trigger could be sent via the resistors to ground....?
Edit: added a schematic...
I am thinking that if Ra>Rb, the energy will have to follow Rb...
Re-edit: I don't need the inverter buffered if Ra>Rb... do I?
Attachments
cathode_leak said:Thanx GM
I have not yet decided wether I'm going to attempt an VCXO circuit myself, but I am concidering it. SMT design isn't exactly my alley, but I realize there are no good reason for not surface-mounting a VCXO circuit. I have friends very capable of SMT mounting, so I'll let others take care of the difficult soldering..
Say I'll take your advice and goes for the ADF4116 PLL... Could you advice a good low-jitter VCXO to go with it, that does not have an internal ground resistor? 'cause I would really like to avoid any digital filter...
In all my years of PLL design, I've never actually used an off-the-shelf VCO or VCXO. Normally I've got some sort of weird frequency requirement, which means that the part needs to be custom made and I can throw in my own specifications.
I've used Raltron, Tech-Time, VF Technologies and Crystek parts, and I've been very happy with all of them. Fox Electronics is well respected, but I haven't used any of their stuff - they're a big company and they don't like making less than a thousand of anything.
I doubt you'll find a 1.411MHz (32*fs) VCXO, but something like 11.289 or 22.579MHz should be easy to find. In this case, you'll have to divide the output of the VCXO by 8 or 16.
I'd search through a few electronics catalogs (digikey, mouser, arrow, allied, etc) until you find a stock VCXO with the frequency you want. Once you get a few part numbers, start looking through datasheets... and if you find one that stands out, e-mail the manufacturer about input resistance and input capacitance. Sometimes they'll even give you a schematic of the varactor circuit, which is a great help.
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