Classic op-amp schematic

[scott wurcer]

I am cleaning my office and found my stash of "ancient" reverse engineering projects. This is the BB3554, it was near the top in its day ~1979. These product are now obsolete and there is no longer any IP interest. I thought some of you might enjoy seeing where folks were back then, in some cases not too far off from were things are now. This was in a BIG 12 pin TO-3 can (note the BeO substrate).

 

[Steve Eddy]

Was this a hybrid circuit?

se

 

[scott wurcer]

Was this a hybrid circuit?

se

Big hybrid discrete. I have some scary ones with comp caps all over.

 

[PMA]

Wow!!!!

I used the BB3554 in 1982, for squirell-cage 63kA shunt active compensation. I got 2MHz bandwidth from that combo. The shunt used for development of SF6 HV circuit breakers, measurements of post-arc currents after zero (interruption).

I still have documentation and scientific report.

 

[PMA]

No kidding, here it is:

(P.S.: If I was to write my professional memories, it would be probably more juicy than those of John ... )

 

[PMA]

The shunt. In the deep dark times of iron curtain, I used Tek556 and Tek7844 dual beam scopes here.

 

[PMA]

Further "classiscs"

 

[Fanuc]

Bootstrapped jfet input cascode on BB3554

Hello,

Thanks for posting the schematic Scott. I was actually looking of using a jfet input cascode that is bootstrapped for a amp circuit like this chip.

I think that Q3 and Q4 cascode jfets must have higher Idss than the input Jfets Q1 and Q2 and higher Vp. This is going by some other jfet self biasing circuits I have seen though I don't know about other pre requisites.

Just out of interest does anyone have any references or experience with this arrangement ?

Thanks

 

[scott wurcer]

Re: Bootstrapped jfet input cascode on BB3554

Hello,

Thanks for posting the schematic Scott. I was actually looking of using a jfet input cascode that is bootstrapped for a amp circuit like this chip.

I think that Q3 and Q4 cascode jfets must have higher Idss than the input Jfets Q1 and Q2 and higher Vp. This is going by some other jfet self biasing circuits I have seen though I don't know about other pre requisites.

Just out of interest does anyone have any references or experience with this arrangement ?

Thanks

The data sheets should be available on line somewhere. I think the FET second stage take off is key (for almost infinite current gain). Virtually no one has done this in IC's, probably for headroom issues.

Tomorrow I will post the most horrifying schematic I found.

 

[PMA]

Datasheet is easily found by google, the Maxim part.

 

[h_a]

Thanks a lot for posting that schematic, Scott!

It is always amazing to get a bit of insight into opamps.

Cool

Have fun, Hannes

PS: stunning that one could do 1nF caps within the IC?? Doesn't take that a lot of space?

EDIT: amazing little amp. No reason why one shouldn't spice up the output stage (VBE-multi to get into ClassAB) and have a nice amp even today.

 

[Steve Eddy]

Re: Re: Bootstrapped jfet input cascode on BB3554

Tomorrow I will post the most horrifying schematic I found.

Well....? It's tomorrow.

se

 

[scott wurcer]

Classic No. 2

OK todays offering is a TP1430 from now defunct Teledyne Philbrick the same people that brought you the first modular tube op-amps. I don't think Bob Pease worked on this, but it has some scary feed-forward. Note again extensive use of FET's. Remember these are modular products built on substrates with all discrete devices the same ones we use for DIY but in chip form.

 

[scott wurcer]

OK one more

Again from Teledyne, this one's really wild, DMOS FET's! Can anyone figure out what the DMOS on the input is doing? It could be some neutralization. 2GHz GBW and 1200V/us. It took years for IC's to catch up to this.

 

[PMA]

How about Analog Devices 46? ILC HVA-23?

 

[gl]

Hi Scott,

This is a wonderful thread. Thank you for sharing all of this information.

What's going on with the Source and Drain connections on the tp1430 input JFET's?

Cheers,
Graeme

 

[scott wurcer]

Hi Scott,

This is a wonderful thread. Thank you for sharing all of this information.

What's going on with the Source and Drain connections on the tp1430 input JFET's?

Cheers,
Graeme

I think I know that one. source and drain reversible. On these dice the order was in a circle GDSGDS so bonding probably made more sense that way.

 

[scott wurcer]

How about Analog Devices 46? ILC HVA-23?

Sorry PMA I only have a faded model 44/48 schematic that won't scan, but I do have the classic Model 50 which is close. Kitted up with hand selected resistors. I remember when we bought FET's that were matched in waffel-packs and sometimes an operator would spill them and just put them back at random.

 

[PMA]

Thanks. Yes, it is close to 46, but different input stage. I may scan the 46 later.

 

[gl]

Thank you Scott. That makes perfect sense.

The M50 schematic is fascinating. With the exception of the current mirror it looks like a Threshold design from the late 70s or early 80s. Great minds....etc.

Graeme