cfp - variant --> current coupled

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No advantage

Stee, sorry to say, but it doesn't work the way you claim it does.
I have simulated the circuit from post 27. Well, of course it does not work "as is" - DC regimes are not correct, as Jan has already mentioned above. But even after some tuning - and making it at least passing the signal through - those "a la diode" pairs don't bring any advantages. Neither stability, nor linearity.

As an example of the working circuit - with the diamond, current mirror VAS and CFP - see >HERE<

It makes sense to at least calculate the values for setting the right DC currents and biases in the circuit before publishing, even if you publish a "conceptual" design, otherwise it is simply "misleading".

Cheers,
Valery
 
SUPREME

SOLUTION:drink:
 

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All those B-C transistors - they are diodes. I would use this to negate a known
thermal co-efficient of a similar vbe (transistor) .

I do look at these threads ... because something "outside the box" (italian wine and TN moonshine)
might pop up.

Still , I am generally confused ?? :confused:
PS - check out my "diamond" , you will see it in real life on a greek workbench.
OS
 
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Stee

With apologies, I can't find inspiration here... to build... or even simulate further. I can't make sense and I even disagree, mostly along the lines of the other posters.

One exception is the function of Q3 of post 3. At first, even before I read the other's posts, I doubted the function of Q3. Does nothing? I mostly think it does nothing but the exception might be that it could affect the dynamic capacitance seen by the feedback transistor between its input and output (however Cbe of Q3 diode is shunted by the diode action and so the effect should be miniscule). On the other and, delta Vbe is twice what it would be, affecting the equivalent of miller effect, which barely exists to begin with since this is almost common collector. Delta Vce of Q1 is dominated by far by the input voltage swing. So again, I don't think so. Nothing here.

Also, simulators do in fact show stability tendencies when AC analysis is used.

Charlie
 
I was interested in CFP OPS, but not any more. Although it offer extra linearity than EF OPS, it also has its drawback. Because of the existence of local feed back, CFP OPS is much slower than EF OPS. That means I have to use lower unit-loop-gain frequency to get the entire amplifier stable. With extra phase margin of using EF OPS with modern transistors, I can implement TMC (Transitional Miller Compensation) without any concern. On one of my amplifiers, I can even stretch its unit-loop-gain frequency to 5MHz! I tried to use CFP OPS to replace EF OPS, it's not just gonna work.

The 1st problem: it is hard to let CFP 100% stable. It's prone to ring even it is stable. Any attempt to compensate/degenerate CFP will kill it's speed/bandwidth. Leave you less phase margin you could work with on the entire amplifier.

The 2nd problem: CFP is a fast-on / slow-off device by nature. Its turn-off speed is much slower than its turn-on speed. It can short the +/- power rail when it goes into high frequency oscillation.
 
I do not have scheme for that amp on hand, but it is based on douglas self's blameless amplifier. The changes is rather little.
It is TMC with EF2 OPS, total 23dB close loop gain, TMC transitional frequency point is set to 1.4MHz, if I looked at its loop gain, the unity-loop-gain frequency was about 3MHz. I played with miller cap and the TMC switch point. Got it run on 5MHz unity-loop-gain frequency was not a problem.
Power Transistor: 2sc5200 2sa1943. Driver: KSC2690A KSA1220A.
I believe you should have gotten the idea what's the scheme look like.
 
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