Protection from high voltage is a reason often used when cascoding. I won't do the subject proper justice, but as NP explains it in posts and his articles, cascoding is often (always?) good. It puts the cascoded device into a flat operating range, and also allows one to "dial in" the sweet spot. If you take a look at NPs sweet spot article, you'll see a place where he suggests a trim pot to allow one to make easy adjustments to find the sweet spot.
So, at lower voltages, cascoding seems to give one a flatter response, and allows for the easier dialing in of the true sweet spot.
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I forgot to comment on your point about the heat sinks and the rail voltage.
I'm a neophyte, so I may be a little off base here. As I understand it, in many of NPs designs, a higher rail voltage doesn't get you much from a Class A perspective. More Class A comes with more bias current. Class AB comes with higher voltages. If one wants high power in Class AB, high rail voltages will get you where you want to go. As I looked at this amp, NP recommended rails of 12V! he issue is staying in the flat response area of the MOSFETs. The Toshiba's are pretty happy at 12V and 16V. The IRFPs are not so happy in that range.
So, if you want a super Class A amp, seek the lowest voltages where outputs that are in a flat response range, then bias, bias, bias! The big story with this amp is the use of the 2SK1530/2SJ201. Now with the less expensive 2SK3497/2SJ618 pair, there's an interesting potential outcome.
No doubt. I read what NP had to say:
http://www.diyaudio.com/forums/pass-labs/129040-mosfet-output-stage-capacitance.html
It's not clear to me that the new outputs will be better - about 2.5x Forward Transfer Admittance and 2.5x Ciss - maybe a wash? They seem a drop in replacement as their Vgs is in the same range.
I'd take advice.
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I know Sokeris has played with them a bit. Accuphase uses them in their Class A amps. Up until now, I think they've been hard to get. I don't know of anyone on the DIY forums in the US that's posted on them - Sokeris is in Denmark.
To quote Sokeris on the outputs:
"And now the Toshiba power mosfets. THD with 100 mA bias don't look to good but are mostly 2nd harmonic. Output impedance is 0.35 ohm with 0.1R source resistors, close to the Bipolars thanks to their high Yfs. But with higher bias they really shine, 300 mA get them into the linear range and now they look very good. But power bandwidth is only 132 Khz and THD increases with frequency, reaching 1% at 20 Khz. As Cgd is dominant over Cgs then paralleling more pairs will just make it worse. A single pair could be used with higher drive current, but a current driver stage is really needed for good results, then the power bandwidth goes up to 730 Khz and THD don't raise with frequency. With a current driver stage you can also lower current in the voltage amplifier stage, ending with THD <0.2% at 1 db below full power."
I'll match mine tomorrow, and hopefully try them on the weekend. At the very least, I will try them in a Cascoded F5 (not balanced) I have ready.
On the other hand, they may not be anything special. It's hard to know at this point, I'm just excited to have some options.
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Another amp
I guess the question is whether a mid stage is needed.
2SJ618/2SK3497?????????????
http://www5.ocn.ne.jp/~squilla/doc0000/au3j7hpa5.html
I guess the question is whether a mid stage is needed.
2SJ618/2SK3497?????????????
http://www5.ocn.ne.jp/~squilla/doc0000/au3j7hpa5.html
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I clearly remember Nelson's words about a year ago, in original F5 thread "I'm surpriced noone suggest to cascode the Jfet"
well, noone seemed to notice when I pointed at cascode part of the Sweet spot article, so here is a part of it
from Nelson Pass 'Sweet spot' article
Cascoding, Paralleling and Transforming
So what do you do if it's impractical to find the optimal load-line in a given circuit? Occasionally the sweet spot occurs at voltage values that are impractically low, or at currents that are higher than a device can handle for a given voltage. Here are three things that a designer can do to get into the zone.
The first is cascoding, where the gain device is coupled with a Common-Gate / Common-Grid / Common-Base (depending on the type of device!) tube or transistor which adds practically no influence of its own but which allows a more arbitrary DC and AC voltage across the gain device. Here are a couple of examples, using JFETs in both Common-Drain and Common-Source circuits.
The top JFET is the cascode device, and its Source voltage, which will be seen by the Drain of the JFET below it, is set by Vref. The idea is that the cascoding device provides a “voltage umbrella” for the gain JFET, and all manner of voltages can appear at the output of the circuit while the gain device sees all, a portion, or none of it.
well, noone seemed to notice when I pointed at cascode part of the Sweet spot article, so here is a part of it
from Nelson Pass 'Sweet spot' article
Cascoding, Paralleling and Transforming
So what do you do if it's impractical to find the optimal load-line in a given circuit? Occasionally the sweet spot occurs at voltage values that are impractically low, or at currents that are higher than a device can handle for a given voltage. Here are three things that a designer can do to get into the zone.
The first is cascoding, where the gain device is coupled with a Common-Gate / Common-Grid / Common-Base (depending on the type of device!) tube or transistor which adds practically no influence of its own but which allows a more arbitrary DC and AC voltage across the gain device. Here are a couple of examples, using JFETs in both Common-Drain and Common-Source circuits.
The top JFET is the cascode device, and its Source voltage, which will be seen by the Drain of the JFET below it, is set by Vref. The idea is that the cascoding device provides a “voltage umbrella” for the gain JFET, and all manner of voltages can appear at the output of the circuit while the gain device sees all, a portion, or none of it.
Odd that he says the Cds dominates, but of course that depends.
The thing is to have a relatively low source impedance for the fets. Given
the distribution of power in audio, it doesn't seem necessary to actually
have a lot of current available. The Jfets I play with are usually good for
35 ohms or so output impedance, less than the gate stoppers which will
also inevitably be employed.
Odd that he says the Cds dominates, but of course that depends.
The thing is to have a relatively low source impedance for the fets. Given
the distribution of power in audio, it doesn't seem necessary to actually
have a lot of current available. The Jfets I play with are usually good for
35 ohms or so output impedance, less than the gate stoppers which will
also inevitably be employed.
I'm going to give them a try, perhaps even tonight, in the Cascoded Balanced circuit and the standard Cascoded F5.
For those of us with less experience (me), Rs is ~0R2 and Rg is 47R - any concrete pointers? I'm not always the fastest with your generous hints.
A long run for a short slide - but worthwhile...
I've been getting some PMs asking what is going on with the output testing for the amp in this thread.
Some may recall, my only issue with the build was a slight 60Hz hum. I was in such a rush to get the amp together that I overlooked NP's amps and how he places the transformer. I'd put my transformer on the back of the amp. This was the opposite of what NP did, I found out why. With the transformer at the back, the wire with the signal crosses the AC in the transformer twice, picking up noise both times. NP builds with the transformer in back, signal stays relatively unharmed.
I vowed to reverse the build in an effort to get rid of the slight hum. On the evening I went to reverse the innards, I reconnected one side of the CRC PS with the wrong polarity - good bye caps.
It took until last week to get replacement caps. I spent the last few days doing the following:
This is the last step in the proof that one can build the Cascoded Balanced F5 on a budget without compromising quality in the least.
Now I urge you to get building!
I've been getting some PMs asking what is going on with the output testing for the amp in this thread.
Some may recall, my only issue with the build was a slight 60Hz hum. I was in such a rush to get the amp together that I overlooked NP's amps and how he places the transformer. I'd put my transformer on the back of the amp. This was the opposite of what NP did, I found out why. With the transformer at the back, the wire with the signal crosses the AC in the transformer twice, picking up noise both times. NP builds with the transformer in back, signal stays relatively unharmed.
I vowed to reverse the build in an effort to get rid of the slight hum. On the evening I went to reverse the innards, I reconnected one side of the CRC PS with the wrong polarity - good bye caps.
It took until last week to get replacement caps. I spent the last few days doing the following:
- Putting the transformer in the front of the case - as outlined above
- Head to toe new star grounding set up
- New rectifiers
- New wiring for the AC in
This is the last step in the proof that one can build the Cascoded Balanced F5 on a budget without compromising quality in the least.
Now I urge you to get building!
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Very interesting thread. I am especially interested in the cascode discussion. Having recently looked into building F3, I had considered other ways to take advantage of the cascose modulation technique. I had thought of implementing it in the BA style amps in the VAS or second stage, using the LU jfets. May not work having not simmed it yet. I am also unsure about how the differential pair would affect the sound normally ascribed to the LU devices.one thing is for sure, if you read all the Pass articles, you have evrything you need to buils a world class amp, that is if someone will buy you a distortion analyzer.
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