Bad marketing and... they did sold to other guys and retired. Like HDCD guys sold to Microsoft and retired.
Sure, those days China would copy anything and reproduce it with their workers paid with pennies. Even here there where questions.
Their product is not dead.
But I think you know better that
Sure, those days China would copy anything and reproduce it with their workers paid with pennies. Even here there where questions.
Their product is not dead.
But I think you know better that
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Well there's Orpheus. That existed in parallel with Anagram. As far as I know they're still in business.
But they didn't retire - they went on to build the Berkeley DAC.
Quick question for ya. You cited Anagram Technologies as making serious money. If they're making so much money, why is their website now one of those useless, vacuous link farms ?
Are you seriously suggesting that's more profitable than engineering?
FYI - Anagram's I.P. has apparently been acquired by the folks at: abc-pcb.com
That new (2009) CS2300 is an interesting cip... didn't see it before.
Down to 1Hz PLL filter sounds interesting. And it can take XTALL inputs too (I am thinking about cleaning some existing Xtal/PLL divider jitter).
As for DIR9001 - TI claims 50ps recovered jitter. WM clamis for 8804 the same 50ps... I know that WM says that their part goes down to 100Hz and the "competitor" just to 10kHz... but I don't know if that is refering to TI part
Those 50ps. jitter specs. are intrinsic - meaning, the jitter which would remain even if the incoming signal contained absolutely no jitter. The more important specification to know (IMHO) is each device's incoming jitter suppression mask/template. Wolfson's use of an 'elastic-buffer' (FIFO) should provide far superior suppression of the incoming signal's jitter.
My own view is that their IP was primarily in marketing, rather than engineering. So I'd be interested to know how many customers there are for that.
Where did you find that info about the "FIFO" buffer in WM8804? I cannot find it in the datasheet.
BTW: The buffer is necessary for a complete low-freq jitter elimination. If you want to go down to 1Hz you need to store at least 1 second worth of data - how many bits are in 1 second? 44.1x1000x2x16=1411200=1378kbits=1.3Mbits. That's the minimum buffer you need!
BTW: The buffer is necessary for a complete low-freq jitter elimination. If you want to go down to 1Hz you need to store at least 1 second worth of data - how many bits are in 1 second? 44.1x1000x2x16=1411200=1378kbits=1.3Mbits. That's the minimum buffer you need!
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Why? Elliminating the jitter you don't eliminate the music - because the data is in sync with the recovered clock and both have that jitter.
A closer analogy would be Common Mode Rejection - leaves the initial sound clean from the supplemental distortions.
Sure, it would imply a 0.5 seconds delay from pressing the "start" to fill half of that buffer...
Jitter - Wikipedia, the free encyclopedia
A closer analogy would be Common Mode Rejection - leaves the initial sound clean from the supplemental distortions.
Sure, it would imply a 0.5 seconds delay from pressing the "start" to fill half of that buffer...
Jitter - Wikipedia, the free encyclopedia
Wolfson refers to it as an "Elastic Buffer", the functioning of which is described in the below linked 2006 AES paper presenting a new S/PDIF reciever architecture. That paper, which can be found on the Wolfson website under "white papers", undoubtedly descibes the general architecture of both the WM8804 and WM8805. Therein, the Elastic Buffer is described as "essentially a buffer that has asynchronous read and write interfaces". To me, that is describing an asynchronous FIFO, which, along with a fractional-N numerically controlled oscillator, are core elements of a digital PLL. I've not taken the time to understand what Wolfson is doing with that sigma-delta modulator they've also got in there.
http://www.wolfsonmicro.com/documents/uploads/misc/en/A_high_performance_SPDIF_receiver_Oct_2006.pdf
That new (2009) CS2300 is an interesting cip... didn't see it before.
Down to 1Hz PLL filter sounds interesting. And it can take XTALL inputs too (I am thinking about cleaning some existing Xtal/PLL divider jitter).
As for DIR9001 - TI claims 50ps recovered jitter. WM clamis for 8804 the same 50ps... I know that WM says that their part goes down to 100Hz and the "competitor" just to 10kHz... but I don't know if that is refering to TI part
Yes, the CS2300 does sound interesting. In fact, I've wondered why Cirrus hasn't yet integrated it with their CS8416. Seems a highly natural pairing which would more than compete with the Wolfson DIR chips.
No, it doesn't say clear that is/will be implemented...
I think they did implement the fractional PLL, but I didn't see any reference in the 8804/05 to the absolutelly necessary FIFO buffer described in the white paper.
Actually, they say "S/PDIF recovered clock using PLL, or stand alone crystal derived clock generation."
The device described in the white paper would be having the word and there.
Also in the datasheet they don't say nothing about a buffer. External clock it just "helping" the PLL loop, but the loop is still specified as beeing locked on the incoming signal.
The buffer would allow the asyncron functionality of the receiver, decoupling the input PLL loop from the XTALL generated output.
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