Well, Self has the Class XD also!!! Doesn't matter it's no more advantage in terms of heat dissipation than heavier biased Class AB....Oh, I mean "Self Class B", need more high power components and more heatsink space. But it is Self!!! He even got a patent too!!!
Oh, someone might look at this. In Class AB with 1A bias, we have up to 2A drive where it is still running in Class A. For 8ohm load, that's 16V, power =0.5 X 16V X 2A=16W of Class A. But with Self Class XD with 1A current source. I cannot figure out how it can be 2A drive in Class A. Seems like Self Class XD has only 1A drive of Class A. If that is the case, Self Class XD use more components, burn more heat AND have ONLY 50% the advantage of just simply bias higher to get a bigger Class A region.
Then why stop here? Class A is defined as 100% conduction. BUT since device does not turn on and off sharp. Maybe the next step is to define "Self Class A" that cover conduction of 95% to 100%. This implies a Self Class AB is from say 52% to 95%. That completes the Self's definitions.
BTW, people including me have been using a resistor pulling to negative rail at the output of the opamps to force the output of the opamp to run at class A. There is no consequence on this because it's low power. This is nothing new. I sure have never consider calling Alan Class XD.
Oh, someone might look at this. In Class AB with 1A bias, we have up to 2A drive where it is still running in Class A. For 8ohm load, that's 16V, power =0.5 X 16V X 2A=16W of Class A. But with Self Class XD with 1A current source. I cannot figure out how it can be 2A drive in Class A. Seems like Self Class XD has only 1A drive of Class A. If that is the case, Self Class XD use more components, burn more heat AND have ONLY 50% the advantage of just simply bias higher to get a bigger Class A region.
Then why stop here? Class A is defined as 100% conduction. BUT since device does not turn on and off sharp. Maybe the next step is to define "Self Class A" that cover conduction of 95% to 100%. This implies a Self Class AB is from say 52% to 95%. That completes the Self's definitions.
BTW, people including me have been using a resistor pulling to negative rail at the output of the opamps to force the output of the opamp to run at class A. There is no consequence on this because it's low power. This is nothing new. I sure have never consider calling Alan Class XD.
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Early effect and SPICE modeling
Let’s talk about Early effect – and how well SPICE models it.
Several posts ago Doug Self stated, “The approximations in SPICE are well-known. (Early effect being a prime example).” He did this in the context of suggesting that SPICE models Early effect poorly and that renders SPICE of limited use in simulating amplifiers accurately.
His assertion bears scrutiny, and in fact I think he is largely wrong. For those with a copy of his 6th edition, I encourage you to read his section on VAS Early effect, pp. 174-179 & Figs 7.13.
Early effect is basically a variation of current gain (beta) as a result of Vce changes. It is theoretically described and modeled in SPICE as a linear variation of beta as a function of Vce.
Early effect results from base width modulation by the collector-base voltage. As Vce increases, the depletion regions on both the base and collector sides of the base-collector junction increase, causing the width of the active base region to become smaller. All else remaining equal, the current gain of a transistor increases as the base width gets smaller. In simple terms, minority carriers spend less time crossing the base and have less opportunity for recombination. Less recombination in the base region means less base current and more current gain.
For modern transistors, beta is accurately described as a linear function of Vce. It is proportional to 1+Vce/VA, where VA is the Early voltage. If Vce were to increase to be equal to VA, beta will have doubled. It is easy to see this straight-line relationship in the Ic vs. Vce transistor plots where base current is a parameter. The upward slope of the Ic vs. Vce curve for a given base current represents the effective output resistance of the device. To the extent that these lines are straight, output resistance is constant with Vce if base current is held fixed. SPICE properly models the relationship of beta to Vce. Put another way, SPICE properly models the linear increase in collector current with Vce when base current is held constant. It can also be seen that the slope is steeper for higher base currents, correctly showing that the effective output resistance of the device is smaller at higher current.
BTW, some point out that the proper variable is actually Vcb, not Vce. This makes sense because it is actually Vcb that is reverse-biasing the collector-base junction. The difference is minor. SPICE actually uses Vcb.
I have not been able to find any learned references where there is discussed a theoretical basis for the (1+Vce/VA) relation being flawed. SPICE follows this relationship perfectly. If one takes issue with this, it is with the device theoreticians, not the SPICE simulator.
This relationship is quite accurate as long as the transistor is not operating near the quasi-saturation or high-level injection regions. See Horowitz and Hill, The Art of Electronics, Third Edition, pp. 92-93 and Fig 2.59 on page 101. Horowitz states, “The computer circuit-analysis program SPICE includes accurate transistor simulation with the Ebers-Moll formulas and Gummel-Poon charge models.” See also Sedra/Smith, Microelectronic Circuits, Sixth Edition, pp. 371-375 and Eq. 6.18. See also Massobrio and Antognetti, Semiconductor Device Modeling with SPICE, 2nd Edition. Chapter 2.1 in my book also covers Early effect.
Self shows a family of output characteristics in Fig 7.13 where the curves bend up at high Vce, presumably supporting his assertion that the Early effect is rather nonlinear. A look at most transistor curves shows this to be a very unusual case. Actually, because of junction temperature effects on beta and saturation current, combined with the short thermal time constant of a small-signal transistor’s junction, it can be very difficult to properly create such curves without errors from thermal effects, even with pulsed measurements of surprisingly short duration. Such thermally-induced errors can cause the Ic – Vce curves to turn upward at higher voltages. Note in Self’s Fig. 7.13, instantaneous dissipation is 10W where the curves begin to turn up significantly. The plot also does not show whether the parameter is base current or Vbe, although I am not sure how big a difference this would make. Take a look at the Ic-Vce curves for the Sanyo 2SA1016, for example. Or the 2SC3503. Unfortunately, and somewhat surprisingly, many datasheets do not show the Ic vs. Vce curves.
Any circuit where small-signal gain depends on beta will exhibit distortion from the Early effect, since gain will be changing as a function of signal voltage and that is synonymous with distortion. The open-loop gain in a classic three-stage power amplifier is strongly dependent on the beta of the VAS transistor, so distortion results.
Bottom line: SPICE modeling of Early effect is more than adequate for high-performance amplifier design simulations – as long as a reasonable value for VA is used in the transistor model.
Cheers,
Bob
Let’s talk about Early effect – and how well SPICE models it.
Several posts ago Doug Self stated, “The approximations in SPICE are well-known. (Early effect being a prime example).” He did this in the context of suggesting that SPICE models Early effect poorly and that renders SPICE of limited use in simulating amplifiers accurately.
His assertion bears scrutiny, and in fact I think he is largely wrong. For those with a copy of his 6th edition, I encourage you to read his section on VAS Early effect, pp. 174-179 & Figs 7.13.
Early effect is basically a variation of current gain (beta) as a result of Vce changes. It is theoretically described and modeled in SPICE as a linear variation of beta as a function of Vce.
Early effect results from base width modulation by the collector-base voltage. As Vce increases, the depletion regions on both the base and collector sides of the base-collector junction increase, causing the width of the active base region to become smaller. All else remaining equal, the current gain of a transistor increases as the base width gets smaller. In simple terms, minority carriers spend less time crossing the base and have less opportunity for recombination. Less recombination in the base region means less base current and more current gain.
For modern transistors, beta is accurately described as a linear function of Vce. It is proportional to 1+Vce/VA, where VA is the Early voltage. If Vce were to increase to be equal to VA, beta will have doubled. It is easy to see this straight-line relationship in the Ic vs. Vce transistor plots where base current is a parameter. The upward slope of the Ic vs. Vce curve for a given base current represents the effective output resistance of the device. To the extent that these lines are straight, output resistance is constant with Vce if base current is held fixed. SPICE properly models the relationship of beta to Vce. Put another way, SPICE properly models the linear increase in collector current with Vce when base current is held constant. It can also be seen that the slope is steeper for higher base currents, correctly showing that the effective output resistance of the device is smaller at higher current.
BTW, some point out that the proper variable is actually Vcb, not Vce. This makes sense because it is actually Vcb that is reverse-biasing the collector-base junction. The difference is minor. SPICE actually uses Vcb.
I have not been able to find any learned references where there is discussed a theoretical basis for the (1+Vce/VA) relation being flawed. SPICE follows this relationship perfectly. If one takes issue with this, it is with the device theoreticians, not the SPICE simulator.
This relationship is quite accurate as long as the transistor is not operating near the quasi-saturation or high-level injection regions. See Horowitz and Hill, The Art of Electronics, Third Edition, pp. 92-93 and Fig 2.59 on page 101. Horowitz states, “The computer circuit-analysis program SPICE includes accurate transistor simulation with the Ebers-Moll formulas and Gummel-Poon charge models.” See also Sedra/Smith, Microelectronic Circuits, Sixth Edition, pp. 371-375 and Eq. 6.18. See also Massobrio and Antognetti, Semiconductor Device Modeling with SPICE, 2nd Edition. Chapter 2.1 in my book also covers Early effect.
Self shows a family of output characteristics in Fig 7.13 where the curves bend up at high Vce, presumably supporting his assertion that the Early effect is rather nonlinear. A look at most transistor curves shows this to be a very unusual case. Actually, because of junction temperature effects on beta and saturation current, combined with the short thermal time constant of a small-signal transistor’s junction, it can be very difficult to properly create such curves without errors from thermal effects, even with pulsed measurements of surprisingly short duration. Such thermally-induced errors can cause the Ic – Vce curves to turn upward at higher voltages. Note in Self’s Fig. 7.13, instantaneous dissipation is 10W where the curves begin to turn up significantly. The plot also does not show whether the parameter is base current or Vbe, although I am not sure how big a difference this would make. Take a look at the Ic-Vce curves for the Sanyo 2SA1016, for example. Or the 2SC3503. Unfortunately, and somewhat surprisingly, many datasheets do not show the Ic vs. Vce curves.
Any circuit where small-signal gain depends on beta will exhibit distortion from the Early effect, since gain will be changing as a function of signal voltage and that is synonymous with distortion. The open-loop gain in a classic three-stage power amplifier is strongly dependent on the beta of the VAS transistor, so distortion results.
Bottom line: SPICE modeling of Early effect is more than adequate for high-performance amplifier design simulations – as long as a reasonable value for VA is used in the transistor model.
Cheers,
Bob
That's reassuring . I see the greatly decreased distortion when using
a hawksford or baxandall/hawksford cascode for VAS.
When I first started using it , I was told it nearly eliminated the early effect.
Both the simulations and the finished amps outperform a standard VAS (noticably).
So I knew this was at least being modeled. "Adequate" would most likely
depend on whether you were designing space probe circuitry or
a simple feedback amplifier.
OS
Found this for anyone who's interested.
http://www.google.ca/url?sa=t&rct=j...rX1oSyQwUp7tE7Q&bvm=bv.96952980,d.eXY&cad=rja
http://www.google.ca/url?sa=t&rct=j...rX1oSyQwUp7tE7Q&bvm=bv.96952980,d.eXY&cad=rja
See this: http://www.diyaudio.com/forums/soli...lls-power-amplifier-book-525.html#post4363970
There are two conditions under which the linear Early model holds:
a) Low level current injection*)
b) Negligible base width modulation (as you said)
While b) is a mostly a matter of device process (the base doping gradient being the most important), a) is determined mostly by the circuit.
I don't recall Mr. Self being concerned by the non linear Early effect in BC546 (although even that shows some non linear Early effect at high Ic, see the datasheet) used in the input stages. The nonlinear Early effect is very present in power devices, jut take a look at the popular 2SC5200 data sheet. Hence, the non linear Early effect mostly affects the output power stage distortions. I do not believe that Spice, with the current BJT model template, has enough provisions to accurately simulate the distortions of a BJT output power stage. And that's even if the actual models are "improved" by matching the parameters with the datasheets. That's simply an application (I mean, semiconductors at high injection levels) that default Spice implementation was never optimized for. This is why the advanced models, for professional use, are not based on the default templates, but are behavioral nonlinear models, parametrized by the device geometry. We are using such models, they are coming in the kits coming from the silicon foundries.
If the current BJT model template in Spice is good enough for DIY use, that's a matter of opinion, everybody may have one.
*) For those less used to this "semiconductor language", "at low injection level" means pretty much "at low Ic". How "low", depends on the device: what is "low" for 2SC5200 is very high for a BC546. There is no clear cut.
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Can anyone comment on this. I just don't see the Class A region extend beyond 1A in the Self Class XD. This is no more than EF with CCS bottom. If the CCS is sinking 1A you can only pull down 1A max and the CCS run out of steam. Then you get into crossover distortion.
If this is true, this is a big big disadvantage compare and simple Class AB with higher bias setting.
If that what so are saying its true than ccs is not voltage or current modulated, just plain CCS like for OPAmp tircks?
If that what so are saying its true than ccs is not voltage or current modulated, just plain CCS like for OPAmp tircks?
You have to read Chapter 18 yourself. That's my understanding but I want to make sure I am reading right.
The XD idea is to have the crossover displaced from the central region around 0V. Then the signal is less often affected by crossover non-linearities and, due its higher slew rate in the new place of the crossover, this non-linearities may be less perceptible if they ever were when placed around 0 V.
Because you insist of this, you'd be better revisiting your design. With 0.1 ohm emitter resistors for 5 output pairs, even with reasonable matched betas, you are at very high risk of current hogging and, as a result, a good dose of magic smoke. The OPS will probably be stable at idle, but after a good hour at a high power output you will very likely get it.
Also bear in mind that base stopper resistors (divided by Beta) are to be subtracted from the emitter resistors, to find out the effective value. Internal emitter resistance (bond wire and emitter diffusion resistance, to the EB junction) adds to the external emitter resistor.
I would not use less than 0.33 ohm resistors for 5 pairs in parallel, to keep the OPS thermally stable and distribute the currents reasonably uniform. With matched Betas you could probably go as down as 0.22 ohm.
I've seen one commercial design with 0.1 ohm emitter resistors and 10 ohm base stoppers, but it was using older BJT power devices (hand matched, of course, was part of the designer's brand) with likely higher emitter spreading resistance and huge heat sinks. Even so, I was always surprised that the design was considered thermally stable.
There is no difference with heavy idle current that you displace the kink of the curve away from the center. How far you move the kinked area depends on how much idle current you have. This is exactly the same whether you use a CCS to pull in the Self XD or just simply run higher idle current. There is absolutely no difference in the displacement of the kink.
I still have question what is the default biasing and how to set Re without the CCS. If you design as Class B( not self class B), the kink is going to very sharp as shown in Fig.10.31 in p278 of his book. So even though you displace the kink, when you hit the kink, it's going to very sharp. I am sure it doesn't help the sound.
I am using as an example. I use re=0.12ohm. AND I do hand matched the power transistors. I actually have a jig for matching. AND to my big surprise, the MJL3281/1302 worst case mismatch when pull 200mA is 4mV between 3 batches bought from different places. It is so easy to find set of 5 that match to 1mV. I even had a thread
http://www.diyaudio.com/forums/solid-state/275364-mjl3281-vbe-matching.html
to show the result and exactly my method of testing.
This is DIY, you expect to design amps better than you can buy!!! I hand match the input LTP for offset and beta also. I measure every single critical resistor to match to 0.1%. This is MY AMP!!! I even string all the 0.12ohm 3W emitter resistors and drive heavy current through for 2 hours to cook it, then measure the voltage drop of each and pick the ones with the closest voltages before I put into the pcb.
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Totally wrong, you need a refresh in large signal behavior of bipolar transistors. There is a fundamental difference, in that the gm doubling distortion mechanism is no longer in the worst conditions (that is, around zero) but in a position where it's effect is significantly reduced. As strange as it looks, from the same perspective, the more the output stage halfs are asymmetric, the less gm doubling distortions it exhibits.
If you prefer, you can look at this in terms of the output stage (<1) gain. The asymmetrical version (or class XD in Mr. Self definition) has significantly less gain variation around the displaced crossover. I find here some similitude with the tanh principle.
This is not to say I'm in love with XD Class, I believe the improvement it brings is not worth the trouble of complexity and extra heat dissipation, but then this is already a personal opinion.
Sorry, this is not engineering, this is blind gourmet cooking combined with voodoo practices. Your call, still what you are trying to do is bad practice - but I would not expect you to admit this. Good luck and happy smoke.
Wrong. the engineering is using the Oliver's optimization of getting 26mV across the Re. The gravy is to make sure they match. Big difference using 0.12 vs 0.1.
Also, it's engineering that I run only 25V or so for rail to keep the heat down.
Also, isn't it stupid of the book to put that out as an example that you cannot use multiple pairs? why even do that?
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I'll let Mr. Cordell answer this. I guess by now, no one rebut my theory that XD only drive half amount in Class A than simple heavy bias. I get a lot more mileage out of simple heavy bias than XD.
ON has real good matching right out of the tube.
My 3 pair tester amp was "cooked" overnight with .15R @ over 60C.
less than a mV difference between the pairs.
My other 3 .22R 5-pair amps have been run for 7 months now - no issue.
Then the hundreds of other 5 pair amps with .22R and 4.7R stoppers - not
one failure.
If alan is actually matching the ON's , I know at 60-100ma - no issues.
200+ , I don't do that .... who knows.
With my Sanken MT-200's , I ran >250ma just to see how hardy the
devices were. I really let it cook overnight ... actually warmed my
little "workcloset' right up ! Re's all tested the same Vdrop from 20-70C.
That one also has 4.7R stoppers and .22 Re's.
Sanken MT-100's are quite poorly matched , always check them. The 200's
also fall far short of the ON's.
I actually tried to let "magic smoke" out of the Sanken's - Nope , even
at almost 500ma per device. Never saw Waly's scenario - even running a
signal into a load (with the overbias).
OS
My 3 pair tester amp was "cooked" overnight with .15R @ over 60C.
less than a mV difference between the pairs.
My other 3 .22R 5-pair amps have been run for 7 months now - no issue.
Then the hundreds of other 5 pair amps with .22R and 4.7R stoppers - not
one failure.
If alan is actually matching the ON's , I know at 60-100ma - no issues.
200+ , I don't do that .... who knows.
With my Sanken MT-200's , I ran >250ma just to see how hardy the
devices were. I really let it cook overnight ... actually warmed my
little "workcloset' right up ! Re's all tested the same Vdrop from 20-70C.
That one also has 4.7R stoppers and .22 Re's.
Sanken MT-100's are quite poorly matched , always check them. The 200's
also fall far short of the ON's.
I actually tried to let "magic smoke" out of the Sanken's - Nope , even
at almost 500ma per device. Never saw Waly's scenario - even running a
signal into a load (with the overbias).
OS