Bob Cordell's Complementary IPS-VAS topology

[danny92]

Hello Dear Mr. Bob Cordell, and thank you very much for your reply,

I know I should try a BJT design first, but I've bought some MOSFETs (BUZ900/905) and it's difficult in my country to find MJEs, I've attached to this file two Bode plots and one picture of the resistor that limits the emitter/collector current of the helper transistor. Talking about the Bode plots, I'm using the 150 pF capacitor to have a phase margin of 50-55 degrees, in the AC analysis of your example at 0 dB the phase shift is 180 degrees?
Or I'm making something wrong?

PS:
I've also attached a simpler design using mosfets and current loaded VAS.

Thank you very much for your attention,
Best regards,
Daniel Almeida

 

[danny92]

I've forgot to attach the Bode plot of your design,it's now attached to this post, I'm sorry.

 

[smms73]

. Talking about the Bode plots, I'm using the 150 pF capacitor to have a phase margin of 50-55 degrees, in the AC analysis of your example at 0 dB the phase shift is 180 degrees?
Or I'm making something wrong?

Daniel , you have to check the phase margin in the open loop response of the amplifier. I attach a image with the open loop response of your amplifier. the 150pf is clearly to high, as Bob Cordell already said , use 22pf instead.
The phase margin at 29db is not 55 degrees is 90.

 

[smms73]

The simplest way to see the open loop response of an amplifier, is substituting the feedback resistors with a large inductor and a large capacitor as the attach image and then do a AC analysis and measure the phase and response on the (out) net.

As the gain of your amplifier is 29db, you should check that at that gain the phase shift is not higher than 120 degrees for a 60 degrees margin (see the yellow cross at my last post).

Hope it helps.

 

[Bob Cordell]

The simplest way to see the open loop response of an amplifier, is substituting the feedback resistors with a large inductor and a large capacitor as the attach image and then do a AC analysis and measure the phase and response on the (out) net.

As the gain of your amplifier is 29db, you should check that at that gain the phase shift is not higher than 120 degrees for a 60 degrees margin (see the yellow cross at my last post).

Hope it helps.

I generally put a large inductor in series with the feedback resistor on the amplifier output side of the feedback resistor, and inject the test signal through a capacitor to that point, with the normal input of the amplifier grounded. This gives the loop gain of the amplifier, and includes the effects of the feedback netowrk attenuation and any phase shift that occurs at the input to the LTP. With this approach, ULGF is where the measured gain is 0dB. This is where phase margin can be read.

Similarly, where the phase goes to zero degrees (the frequency which I will here refer to as the Inverting Loop Gain Frequency; i.e., accumulated lagging phase shift = 180 degress) the amount by which the gain is less than 0dB is the gain margin. Note that at this frequency, whatever feedback there is, is pure positive feedback, and there will be gain enhancement as a result.

It is important to not ignore gain margin (GM) or view it as less important than phase margin. I like to see at least 10dB of gain margin. This is usually the point at which the closed loop response above ULGF is monotonically decreasing - it may have a "shoulder" or somewhat flat region, however, due to the gain enhancement at ILGF. Often, if you satisfy the GM number of 10dB, the PM will be over 60 degress.

It is very important to look at the closed loop gain up to at least 10MHz. For an amplifier with ULGF of 1MHz, ILGF will often be in the vicinity of 6MHz, and that will also be the frequency range in which the CLG shoulder (or above-band peaking if GM is smaller) can be seen.

Cheers,
Bob

 

[mcd99]

Bob,

This actually answers a question I had asked in my latest thread. Please could you elaborate on what are the danger signs in the plot type in your post above. Also when you talk about an AC current probe test for stability in the next section in your book how is this implemented in ltspice and what would the danger signs be?

PS I don't want to hijack this thread just seemed a good place to ask the questions.

Many thanks

Paul

 

[smms73]

I generally put a large inductor in series with the feedback resistor on the amplifier output side of the feedback resistor, and inject the test signal through a capacitor to that point, with the normal input of the amplifier grounded. This gives the loop gain of the amplifier, and includes the effects of the feedback netowrk attenuation and any phase shift that occurs at the input to the LTP. With this approach, ULGF is where the measured gain is 0dB. This is where phase margin can be read.
there will be gain enhancement as a result.

That is a very good way of doing it , I normally use the Tian loop gain probe, but your idea is easier. Thanks very much for the tips.

 

[danny92]

Hello everyone,
and thank you very much for your help

I don't understand what I've to do to calculate the gain and phase margins, I've tried to do the circuit that Bob suggested, but I don't understand the results. I've noticed has Bob said in the LTSpice tutorials, that the vb2 (inverter transistor base voltage of the ltp) AC analysis shows peakings when instability occurs, in my case with 29dB closed loop gain this happens for CMiller values inferior to 10pF.

I'm thinking about using a CMiller capacitance between 15 and 33pF, it's a good idea?

PS: I'm sorry, those examples use a Bob Cordell based topology, but are not a IPS-VAS topology, because I'm trying to understand gain and phase margins, then I will apply the same principles to the IPS-VAS topology.


Can you please help me here?
Best regards,
Daniel Almeida

 

[Dave Zan]

First, there is the issue of VAS idle current from one amplifier to the next when no adjustment is provided for each amplifier (something one definitely does not want to do). Secondly is the temperature stability of the VAS current in a given amplifier....

With regard to temperature stability, if the main VAS transistor heats up and its Vbe decreases, VAS standing current will be increased. This effect is reduced in proprtion to the amount of VAS emitter degeneration. I would not recommend having less than 300mV across the VAS emitter resistor if this circuit is to be used...

I was surprised to discover that increased Current Mirror emitter resistors actually decrease noise.
Should not be an issue for the VAS but I would now like to understand how increased VAS emitter resistors alter noise.
And how the increased CM resistors would interact with VAS resistor values to affect current stability.
My hope is to reduce noise and actually improve current stability by increased CM emitters and appropriate VAS emitter choice.
To minimise other impacts I assume precision resistors, probably decreased LTP resistors to make up gain loss, and boosted rails are available so extra potential drop is not of concern.

I should mention one more thing in connection with the current mirror "helper" transistor. I am less enamored of it than I used to be, as its use appears to cause a bit of peaking in the open-loop response when used in conjunction with a VAS preceded by an EF...

Just when I was convinced to use it
It would be nice to keep the gain and just kill the peak but a base stopper or emitter resistor looks to mess up the balance a bit.
It would be helpful to better understand where the peak come from.
Presumably the helper transistor gyrates the ?? impedance into... uhm...?

Best wishes
David

A small base stopper should have minimal effect I think.

 

[wahab]

Hi whab, thanks for clarifying this.

To the first point, the base-emitter drop across the mirror helper elevates the DC voltage level on both sides of the current mirror so that the collectors of the two mirror transistors will now be at the same potential (2Vbe+VRE of the helpered VAS transistor). If the two collectors of the mirror were not at the same potential, current would flow through the 100k at rest, creating an undesirable offset. Vcb on both sides of the current mirror is 1Vbe.

I see what you mean about connecting the collector of the mirror helper to the emitter of, e.g., Q4. However, I usually like to flow some reasonably determined current through the helper (beyond the base current of the 2 mirror transistors) to keep its ft up. This current flowing in the emitter of Q4 would upset the balance of the diff pair. Connecting the collector of the helper to ground does not allow it to draw large currents in practice because the current of the associated mirror transistor will always increase sufficiently to cause self-limiting to occur (i.e., rise to be greater than the maximum current that Q4 can source, which is the tail current).

Cheers,
Bob

Hi Bob ,

Actualy LTPs pairs currents seems more balanced when connecting
the helper to is driving transistor emitter.

If it s connected to ground then the helper will add a current
coming from ground to the left side (output node) of the current mirror
hence increasing the error.

 

[Bob Cordell]

I was surprised to discover that increased Current Mirror emitter resistors actually decrease noise.
Should not be an issue for the VAS but I would now like to understand how increased VAS emitter resistors alter noise.
And how the increased CM resistors would interact with VAS resistor values to affect current stability.
My hope is to reduce noise and actually improve current stability by increased CM emitters and appropriate VAS emitter choice.
To minimise other impacts I assume precision resistors, probably decreased LTP resistors to make up gain loss, and boosted rails are available so extra potential drop is not of concern.



Just when I was convinced to use it
It would be nice to keep the gain and just kill the peak but a base stopper or emitter resistor looks to mess up the balance a bit.
It would be helpful to better understand where the peak come from.
Presumably the helper transistor gyrates the ?? impedance into... uhm...?

Best wishes
David

A small base stopper should have minimal effect I think.

Hi Dave,

Increased CM emitter resistors degenerate the CM and reduce noise gain in the arrangement. When there are no other considerations, I usually degenerate things by 10:1, meaning the emitter resistor is on the order of 10X the dyamic resistance re (1/gm) of the associated resistor. This often puts about 300mV across the emitter resistor.

Use of 1% resistors is definitely advisable here.

Yes, the presence of the CM helper transistor is something that came up recently and still has me scratching my head a bit. I have generally been an advocate of the helper in the past, along with a small bleeder resistor to establish its collector current at a value at least 10X the amount of the base currents of the CM transistors.

I think that what I was seeing was a reduced amount of gain margin.

Cheers,
Bob

 

[gepard_120]

Hello Mr. Cordell, hello other Readers,

Today I built the circuit in Question "Figure 7.10 Complementary differential input stage with stabilized current mirror loads.", (page 139 in Bob Cordells Book), and I observed a very large drift in VAS standing current, (about +/- 50%) as it has been mentioned in the first posting of this thread. The circuit appeared to be useless at the first glance.

Then I doubled the values of the two 470R resistors and the value of the 1K resistor. After this modification, the current was quite stable, the circuit has become usable. Now the VAS standing current is mostly defined by the voltage drops on the RESISTORS and less by the voltage drops on the semiconductor junctions.

I'm planning to increase the resistor values even more, to gain more stability (which I need, because the VAS standing current goes through the ThermalTrak Diodes od my output transistors fpr bias compensation, I have a separate powers supply for the VAS, so voltage drop is no issue)

Now I was able to compare the the THD of the conventional LTPs loaded with resistors and the LTP loaded with current mirrors, the THD (10kHz) goes down to approx. 75% of int's inital value. (Of course, there are some other topics in the amplifier to be worked on, this number has no general meaning, some THD reduction may be masked by other issues)

Best Regards

Henry Westphal

 

[nattawa]

Congratulations!

Inspired by Bob's Figure 7.10 I designed and built my own flavor of the full complementary amp too. I used dual transistors in the input stage and the current mirrors for their matched parameters and good thermal coupling. I have had little fluctuation to the VAS standing current. This is the link

If you have not already been using it, I would recommend this two-transistor bias tracker that is pretty much immune to the fluctuation of VAS standing current. My amp has ThermalTrak output transistors too, and this circuit has produced a very stable OPS bias current.

In this circuit the 2nd transistor would bypass most of the VAS standing current fluctuations so that they don't go through the ThermalTrak diodes and the temperature sensing transistor, which would otherwise cause the bias current of the OPS to fluctuate along. The bias adjustment in this circuit will not affect the bias voltage tempco, which is another merit.