Bob Cordell Interview: BJT vs. MOSFET

[x-pro]

PS We may agree nonetheless, from the standpoint of crossover performance, that there is a substantial difference in having the anti phase device completely cutoff or idling at some nonzero current.

This is particularly relevant in global feedback arrangements, where a susbstantial surge in drive can be observed, trying to quickly bring the cutoff device into operation. It was this fact that brought my attention on the issue.

Rodolfo,

I would completely agree with you on that point. It is useful to remember, that the actual operation of a circuit does not depend on how it is called .

Alex

 

[Bob Cordell]

I agree that Class AAB makes sense. The point that I wish to make is that if an amp is mostly working in the Class A region for normal program material, and most of the time, then the Class A region should be considered dominant. However, if a circuit is biased so that it is going through a transistion to Class B more than 50% or so of the time, then it is Class B, mostly. Still, pure Class B can be defined as 90-100% of the time, so that is yet another case. So, I guess Class B to Class AB to Class AAB to Class A is OK with me.

Sounds good to me.

Bob

 

[Bob Cordell]

Mr. Curl, Mr. Cordell


Though this may sound picky on details, I belive there is a definite difference among class AB (and B) where one half is allowed to cut off completely during part or all of the opposite cycle, in comparison with a topology where even during the opposite cycle there is a controled amount of current (not following the signal as is the clase for class A).

Perhaps the concept deserves a designation of its own, and the dividing line is not really a certain amount of current but a fundamentally different mode of operation bridging class AB-B with class A.

Rodolfo

PS. AAB points in the general direction

Yes, you are basically referring to what many of the sliding bias circuits do. A good modern example of the is the LT1166 driver. I would not add yet another class name, but just add a modifier, like sliding bias.

Bob

 

[Bob Cordell]

Mr. Curl,

Yet I find there is a subtle - or not so subtle - difference on the possible interpretations of class AAB. To put it more clearly, the standard definitions, and what should be debated.

- Class A - Both devices reproduce the same signal in opposite phase.

- Class B - Only one device conducts on each half cycle, the anti phase one being cutoff.

- Class AB - Both devices operate as in class A within a (small) overlapping region, and are respectively cutoff during part of the cycle.

Now for class AAB.

Alternative 1. - Same as class AB, only the region of overlap is substantial whereby at low signal levels operation si truly class A. Full cutoff still holds for a small to moderate part of the cycle for higher power levels.

Alternative 2. - Like class AB, only in this case special means are provided so as to prevent full cutoff at any power level. The minimum anti phase current may be anywhere from usual class AB quiescent bias, to something like the quiescent bias for Alternative 1.

Rodolfo

Alternative 2 just adds confusion. See my comments above.

Bob

 

[forr]

A classification which is not ambiguous:
Class A : at any time, both devices are conducting simultaneously.
Class B : at any tine, at least, one device is conducting.
Classe C : at any tine, the devices are never conducting simultaneuously.

 

[SpittinLLama]

Now if we could just nail down what Class G and H mean Never mind 'marketing' classes like class I and T.

-SL

 

[Nelson Pass]

Or Class XD

 

[Edmond Stuart]

Let'g go back to the previous topic: modeling of the capacitances of a power MOSFET, far more interesting than a semantic debate on class-AAB, AAAAAB, ABB or class-BLAH-BLAH.

Cheers,

 

[andy_c]

Let'g go back to the previous topic: modeling of the capacitances of a power MOSFET

Yes, there's a lot to this subject.

I am just now re-reading the MOSFET chapter of Massobrio and Antognetti and found a reference to the Cgs "jump" at the threshold voltage that Alex has been talking about. They give a reference to Meyer [1] for this effect (not the Meyer of Gray and Meyer fame).

Massobrio and Antognetti talk about the simulation errors this model causes. They say "The transient current calculated in Eqs (4-70) to (4-77) are also functions of the time step, while in the quasi-static operation hypothesis, the charge is only a function of the voltages. This problem causes errors in the simulation of circuits where some nodes in the network cannot change their charge..."

They mention that the problem is mostly solved by using a charge-controlled model due to Ward [2, 3]. They give the charge equations, and then state, "This approach is not justified from the physical point of view...". But that's what SPICE uses for the NMOS and PMOS models. I can't see any explicit formula for Cgs in the Ward model, as the use of charge seems to obscure things. There are only explicit formulas for Cbs and Cbd where "b" is the body.

The Cgs vs Vgs characteristic "jump" in Meyer's model is referenced to lateral MOSFETs, and it's not clear to me whether or not this applies to verticals. So far, I haven't found much good information on this regarding verticals, with the exception of the Fairchild application note AN-9010. In that app note, the author talks about a small variation of Cgs with Vds but apparently does not address the issue of Cgs vs Vgs. I need to read this app note more carefully. It appears to be quite good at first glance.

Edit: Here's another reference relating to lateral MOSFETs that may help: http://media.wiley.com/product_data/excerpt/96/04714986/0471498696.pdf

[1] J. E. Meyer, "MOS Models and Circuit Simulation", RCA Review. 32, 1971

[2] D. E. Ward and R. W. Dutton, "A Charge-Oriented Model for MOS Transistor Capacitances", IEEE J. Solid-State Circuits, SC-13, 1978

[3] S. Y. Oh, D. E. Ward, and R. W. Dutton, "Transient Analysis of MOS Transistors", IEEE Trans. Electron Devices, ED-27, 1980.

 

[Bob Cordell]

Yes, there's a lot to this subject.

I am just now re-reading the MOSFET chapter of Massobrio and Antognetti and found a reference to the Cgs "jump" at the threshold voltage that Alex has been talking about. They give a reference to Meyer [1] for this effect (not the Meyer of Gray and Meyer fame).

Massobrio and Antognetti talk about the simulation errors this model causes. They say "The transient current calculated in Eqs (4-70) to (4-77) are also functions of the time step, while in the quasi-static operation hypothesis, the charge is only a function of the voltages. This problem causes errors in the simulation of circuits where some nodes in the network cannot change their charge..."

They mention that the problem is mostly solved by using a charge-controlled model due to Ward [2, 3]. They give the charge equations, and then state, "This approach is not justified from the physical point of view...". But that's what SPICE uses for the NMOS and PMOS models. I can't see any explicit formula for Cgs in the Ward model, as the use of charge seems to obscure things. There are only explicit formulas for Cbs and Cbd where "b" is the body.

The Cgs vs Vgs characteristic "jump" in Meyer's model is referenced to lateral MOSFETs, and it's not clear to me whether or not this applies to verticals. So far, I haven't found much good information on this regarding verticals, with the exception of the Fairchild application note AN-9010. In that app note, the author talks about a small variation of Cgs with Vds but apparently does not address the issue of Cgs vs Vgs. I need to read this app note more carefully. It appears to be quite good at first glance.

Edit: Here's another reference relating to lateral MOSFETs that may help: http://media.wiley.com/product_data/excerpt/96/04714986/0471498696.pdf

[1] J. E. Meyer, "MOS Models and Circuit Simulation", RCA Review. 32, 1971

[2] D. E. Ward and R. W. Dutton, "A Charge-Oriented Model for MOS Transistor Capacitances", IEEE J. Solid-State Circuits, SC-13, 1978

[3] S. Y. Oh, D. E. Ward, and R. W. Dutton, "Transient Analysis of MOS Transistors", IEEE Trans. Electron Devices, ED-27, 1980.

Thanks, Andy. This is good information. Thanks for jumping back into this discussion, and keep up the good work. I hope we can get a handle on how big the capacitance increase is in an IRFP240 under usual power amplifier operating conditions and how big the error is in SPICE modeling of this, and finally how big the consequent error in SPICE predicting the distortion of an amplifier is as a result.

Can you email me the IRFP240 and IRFP9240 models you were using with the improved LTSPICE simulator modeling capability at bob@cordellaudio.com.

Thanks!
Bob

 

[andy_c]

Can you email me the IRFP240 and IRFP9240 models you were using with the improved LTSPICE simulator modeling capability...

Hi Bob,

For the P-channel device, I was using the FQA12P20, which is the closest Fairchild FET to the IRFP9240. This was to avoid using the P-channel IRF FETs. For the N-channel device, I was using the IRFP244, which is a 250V device whose Id-Vgs curve and gate charge appear to be a better complement to the FQA12P20 than the IRFP240 is. I'll send you the models as well as the Excel spreadsheets that I used to fit the datasheet parameters. I don't have VDMOS models for the IRFP240 or IRFP9240 but I do have the NMOS and PMOS level 3 models of these from PSPICE.

The LTSpice VDMOS model assumes that Cgs is constant. Cds vs Vds is fit using the capacitance of the body diode. Cgd vs Vgd is fit using a formula that's documented in the LTSpice help file.

You have email

 

[x-pro]

Yes, there's a lot to this subject.

Hi Andy,

thank you for all that information - it is very interesting. I am happy that I've provoked this kind of research . It would be good if we can estimate the errors for the distortion calculation, as Bob said. Appnote from Fairchild is indeed very thorough and thought it does not address this issue directly it provides good pictures illustrating formation of the channel in a MOSFET and makes it clear how this additional capacitance is created. As I've said at the very beginning, this effect is well known and described in some literature (I came across such a description in a book on ASIC design and decided to check it for power FETs) . It is quite clear that the effect is not of much importance in a simulation of a switching circuit as it can be accomodated by an appropriate increase in Cgd. In an analogue world, especially in an amplifier simulation this effect could be fairly significant, and I suspect only measurements could give us an indication how significant. Easiest way to look at it so far was to check the gate charge changing with time for a constant gate current and a constant Vds, as in that case any "knee" on the charge curve could only be attributed to that effect in abcence of good old Miller. I will try to make a proper setup for it using a digital scope so different devices could be checked and compared in a range of current and voltages. An obvious advantage of this approach is that it could be done in a single short pulse and so high voltage and current conditions could be easily tested.

Cheers

Alex

P.S. Your second reference:

http://media.wiley.com/product_data/excerpt/96/04714986/0471498696.pdf

is a excellent and deep analysis of the processes in a MOSFET capacitances and it just shows in details how complex is that situation, including frequency dependant effects etc. I am reading it now.

 

[andy_c]

Easiest way to look at it so far was to check the gate charge changing with time for a constant gate current and a constant Vds, as in that case any "knee" on the charge curve could only be attributed to that effect in abcence of good old Miller.

Exactly! The approximations of Meyer and the accompanying graph in Massobrio and Antognetti show a near-zero Cgs below threshold, and almost a step function increase in Cgs at threshold. If that were the case with the IRFP244, I'd expect the gate charge graphs to show Vgs ramping up very fast from 0V to the threshold of about 4V, then with the sudden increase in Cgs at threshold, I'd expect to see an abrupt slope change (smaller slope = bigger Cgs). My skepticism comes from those plots appearing to have a constant slope all the way from 0V to 7V where the current reaches 11A, turning off the diode in the drain circuit and sending the drain voltage downward.

My guess is the phenomenon is probably much more pronounced in laterals than verticals, but I have no rigorous basis on which to make that statement. Your graph of the Hitachi FET showed the abrupt change in Cgs, but I assume that device is a lateral.

 

[x-pro]

I'd expect the gate charge graphs to show Vgs ramping up very fast from 0V to the threshold of about 4V, then with the sudden increase in Cgs at threshold, I'd expect to see an abrupt slope change (smaller slope = bigger Cgs). My skepticism comes from those plots appearing to have a constant slope all the way from 0V to 7V where the current reaches 11A, turning off the diode in the drain circuit and sending the drain voltage downward.

Andy,

here is one of my results for IRL530N:

http://www.diyaudio.com/forums/showthread.php?postid=1191496#post1191496

and it clearly shows a "knee" at the threshold with a constant Vds.

If you do have IRFP240 and a digital scope handy please repeat this experiment - it is very easy to do, I've done it during my lunch break .

Cheers

Alex

P.S. after reading that paper I am quite happy to see that my results are very much in agreement with the theory

 

[andy_c]

In your post showing the measurement, you state:

Note, that the trace is for a constant Vds unlike the traces usually found in the gate charge graphs, where Vd changes and Miller effect is present

Have another look at AN-944, which describes how the gate charge measurements are made. Specifically, look at Figure 4 and the text that accompanies it (section 3, "The Gate Charge Curve"). You'll see that in the leftmost region of the gate charge curve where the Vgs is ramping up, the Vds is constant, except for small variations in the drop across the forward-biased diode as its current varies (see figure 5). In this region, the diode in figure 4 is ON, clamping the drain to a fixed voltage. In the case of the IRFP244, the diode doesn't turn OFF until the drain current reaches 11A (at Vgs ~= 7V). That setup is not the same thing as Fairchild app note AN-7502, figure 4, which implies a resistor in the drain.

Of course, once the drain current reaches 11A and the diode turns off, the Vds is no longer constant. But that's the "flat" part of the curve, and not the part I was referring to.

Further, since the datasheet measurements use a very large Vds (50-200V), the effect of Cgd on Ciss is negligible and Ciss is dominated by Cgs. In your measurements, Vds is 3V, which tends to obscure whether the capacitance variation is due to variations in Cgs vs. Vgs or variations in Cgd with Vgd or some combination thereof.

I'll repeat, it's important to realize that Vds is constant in the entire "ramp-up" region of the gate charge curve. If we can't agree on that, then the conversation will just go around in circles as it has been.

 

[Nelson Pass]

and it clearly shows a "knee" at the threshold with a constant Vds.

No doubt it does. It is consistent with what is already known
about the gradually changing Cgs versus Ids. The sharpness of
your knee in this trace is the combined effect of increasing
capacitance with a logarithmic RC time constant, and so the
nonlinearity of the capacitance is not as great as the curve
suggests.

Charging the Gate with a constant current source or with a
higher voltage pulse through the Gate resistor would reveal a
smoother function.

 

[x-pro]

I'll repeat, it's important to realize that Vds is constant in the entire "ramp-up" region of the gate charge curve. If we can't agree on that, then the conversation will just go around in circles as it has been.

Andy,

if you look at Qg curves in the datasheets you'll see that these are mostly approximated out of strait lines with sharp corners .

We can easily measure this so there is no reason to agree or disagree on theoretical grounds . Let's get some real data and than discuss it.

Cheers

Alex

 

[x-pro]

The sharpness of
your knee in this trace is the combined effect of increasing
capacitance with a logarithmic RC time constant, and so the
nonlinearity of the capacitance is not as great as the curve
suggests.

That is absolutely correct - however the "knee" is there, it is the threshold related effect and the question only - how significant it is in real life, i.e. in an amplifier? There is a difference in sound quality between different FETs and the difference in the gate capacitance behaviour could be one of the reasons for it.

Charging the Gate with a constant current source or with a
higher voltage pulse through the Gate resistor would reveal a
smoother function.

I'm going to do just that and get more different FETs as soon as I can spare some time to do it. If Andy or somebody else would try to set up a similar experiment it would be even better . What I did so far is just to illustrate the existence of such an effect and the simple fact that models commonly used for SPICE simulations are wrong in this respect.

Let's first see what is real size of this effect in most commonly used MOSFETs and than we'll have something to discuss further.

Cheers

Alex

 

[Bob Cordell]

In your post showing the measurement, you state:



Have another look at AN-944, which describes how the gate charge measurements are made. Specifically, look at Figure 4 and the text that accompanies it (section 3, "The Gate Charge Curve"). You'll see that in the leftmost region of the gate charge curve where the Vgs is ramping up, the Vds is constant, except for small variations in the drop across the forward-biased diode as its current varies (see figure 5). In this region, the diode in figure 4 is ON, clamping the drain to a fixed voltage. In the case of the IRFP244, the diode doesn't turn OFF until the drain current reaches 11A (at Vgs ~= 7V). That setup is not the same thing as Fairchild app note AN-7502, figure 4, which implies a resistor in the drain.

Of course, once the drain current reaches 11A and the diode turns off, the Vds is no longer constant. But that's the "flat" part of the curve, and not the part I was referring to.

Further, since the datasheet measurements use a very large Vds (50-200V), the effect of Cgd on Ciss is negligible and Ciss is dominated by Cgs. In your measurements, Vds is 3V, which tends to obscure whether the capacitance variation is due to variations in Cgs vs. Vgs or variations in Cgd with Vgd or some combination thereof.

I'll repeat, it's important to realize that Vds is constant in the entire "ramp-up" region of the gate charge curve. If we can't agree on that, then the conversation will just go around in circles as it has been.

These are very good insights, Andy. I think we all agree that we have to look at this in the absence of Miller effect. Its also helpful to view it in a situation where the expected changes in Cgd as a function of Vdg are not adding a lot of confusion. If the gate charge curve is a straight line up to 11A, as I believe you suggest, and if that curve is accurate (Alex appears to think it is not), then the curve would suggest that the increase in gate capacitance as we pass through threshold, is relatively minor.

Cheers,
Bob

 

[kASD]

Out of all these measurements, I think a Good Emitter Follower with enough low output impedance would eventually take care of all the associated non linearities with all capacitances Ciss,Cgd,Cgs....all you need is a good understanding of mosfets and a basic driver stage for driving Mosfets properly....to fulfil various objectives so far...

Now where the heck is...