Heat transfer and thermal stability
Some results from prototype - transistors from left to right : voltage regulator, VAS, emiter follover, EC/thermal tracking, driver, output mosfets ( 6 x IRF 640/9640 ). All are fitted at gold plated copper prism, which is also power rail conductor. Bias current 250 mA by 20 °C, fall to 235 mA by 60 °C. Bias current after thermal step ( full power cca 30 sec ) rise only a few percent and after cca 3 sec fall to previous value. Do you need more ?
Some results from prototype - transistors from left to right : voltage regulator, VAS, emiter follover, EC/thermal tracking, driver, output mosfets ( 6 x IRF 640/9640 ). All are fitted at gold plated copper prism, which is also power rail conductor. Bias current 250 mA by 20 °C, fall to 235 mA by 60 °C. Bias current after thermal step ( full power cca 30 sec ) rise only a few percent and after cca 3 sec fall to previous value. Do you need more ?
Re: Re: Re: Amazed On Your Opinion
Hi Kanwar,
I apologize for getting your name wrong.
Yes, that APT device may not be a trench FET.
Tell us more about the amplifier you built using it. What kind of distortion performance did you achieve at 20 kHz?
Please explain what you meant by the type of output inductor influencing the reliability of the MOSFET during a short-circuit condition.
Please also explain why you assert that the MOSFET gate must be clamped to a negative Vgs of about -5V for fast turn-off. Is this for protection in a short-circuit condition? How fast are you asserting that turn-off must be in order to have safe short circuit protection?
Cheers,
Bob
Workhorse said:
Hi Kanwar,
I apologize for getting your name wrong.
Yes, that APT device may not be a trench FET.
Tell us more about the amplifier you built using it. What kind of distortion performance did you achieve at 20 kHz?
Please explain what you meant by the type of output inductor influencing the reliability of the MOSFET during a short-circuit condition.
Please also explain why you assert that the MOSFET gate must be clamped to a negative Vgs of about -5V for fast turn-off. Is this for protection in a short-circuit condition? How fast are you asserting that turn-off must be in order to have safe short circuit protection?
Cheers,
Bob
Bob Cordell said:
Hi Bob,
I have previously checked the APT specs a year ago, so insisted upon it that its not a Trench....
In my Class-AB amp...with 20Khz sinewave the output generates only 0.05% THD with amp loaded with 4 ohms, Vcc +-90..
The driver stage is high speed high current opamp based configured as Voltage controlled current source...
It requires no thermal tracking, the Bias setting doesnot even change with variation in temp, Vds[Rail voltage variation]
Drivers have their own floating power supplies...
The normal regular linearly wound inductors are not feasible in preventing the current spikes from destroying the mosfet in event of a direct applied short....The current conduction is so fast that the huge current spikes are generated which exceeds the ratings of mosfets and also at the same time the voltage spikes also produced in the event of SC[To check this apply a direct short with full voltage swing at the output of amp after inductor and monitor the output before inductor with scope & in case of current spikes measure them with current probe in magnetically interfaced with the output]
In normal inductor the magnetic field is losely confined throughout its lengh, but if the inductor is edge wound the MF would confined tightly to narrow area thereby making the Q factor very high....This Edge Wound inductor absorbs the current as well as high voltage spikes much efficiently than the normal one and thus adds the a small delay to the rising of spikes.....It ceases the high di/dt rate of spikes and protects the mosfets from direct short...
In normal inductor the magnetic field is losely confined throughout its lengh, but if the inductor is edge wound the MF would confined tightly to narrow area thereby making the Q factor very high....This Edge Wound inductor absorbs the current as well as high voltage spikes much efficiently than the normal one and thus adds the a small delay to the rising of spikes.....It ceases the high di/dt rate of spikes and protects the mosfets from direct short...
The negative Vgs again turns OFF the mosfet much faster than simply clamping the VGS to Zero....which inturns give the protection circuit a "Relief Time" interval to activate accordingly because the protection would work only when the mosfet would encounter abnormal SC condition....the protection is always slow whereas mosfet damage is much faster...
Also the negative VGS clamping ascertains the robustness of mosfet during false turn-on due to parasitics or miller coupling artifacts arisen from spikes in case of direct short....
The above mentioned techniques costs me about 250 pieces of dead IRFP250N fets which were failed during SCP experimentation purposes ....
Cheers,
Kanwar
Also the negative VGS clamping ascertains the robustness of mosfet during false turn-on due to parasitics or miller coupling artifacts arisen from spikes in case of direct short....
The above mentioned techniques costs me about 250 pieces of dead IRFP250N fets which were failed during SCP experimentation purposes ....
Cheers,
Kanwar
Workhorse said:
This is the inductor that is normally on the order of 1-4 uH. It's effect on speed of events would be measured in microseconds, would it not? I don't think MOSFETs go that fast in a circuit of reasonable design.
MOSFETs WILL go very fast if you punch through the oxide, either by over-voltaging the gate (usually 20V max) OR if you have a parasitic oscillation. But those are issues of proper design, not of short circuit protection.
Moreover, this is the inductor in parallel with which we usually place a 0.5-5 ohm resistor, which actually acts to kill the Q. So if I build an ordinary inductor with the same inductance, same series resistance, and same Q when it has the resistor in parallel, how have I changed the short circuit protection behavior when I build the inductor with the special techniques you describe?
Cheers,
Bob
Hi Kanwar
What do you mean by edge-wound inductor?
Spiral (i.e. planar?)
The point about a linear inductor is that this generally has a low self-capacitance.
Spiral wound inductors are not efficient. The inner turns do not share the same area of the magnetic field as the outer turns.
To protect a MOSFET (or bipolar for that matter) at speed, the inductance is the primary consideration, not necessarily the style.
But layouts of the inductor can vary the parasitic capacitance etc.
I suspect if you want a low parasitic inductor you will need a linear type with perhaps slightly-spaced turns.
Regards
John
What do you mean by edge-wound inductor?
Spiral (i.e. planar?)
The point about a linear inductor is that this generally has a low self-capacitance.
Spiral wound inductors are not efficient. The inner turns do not share the same area of the magnetic field as the outer turns.
To protect a MOSFET (or bipolar for that matter) at speed, the inductance is the primary consideration, not necessarily the style.
But layouts of the inductor can vary the parasitic capacitance etc.
I suspect if you want a low parasitic inductor you will need a linear type with perhaps slightly-spaced turns.
Regards
John
Workhorse said:
Kanwar,
It is true that source ballast resistors of reasonable size (say, <0.5 ohm) do little to help current sharing under idle bias conditions with MOSFETs. The amount that any such resistor helps is dependent on its relationship to the gm of the device it is working with. If 1/gm is large compared to the resistor, the resistor helps very little. if 1/gm is equal to or small compared to the resistor, the resistor helps quite a bit. The ballast resistor doesn't help MOSFET current sharing at Class AB idle bias because at that point 1/gm is typically larger than the ballast resistance.
However, such ballast resistors do help current sharing among paralleled MOSFETs at high currents, where SOA considerations may come into play, and they do lessen the tendency for any one MOSFET to current-hog under these conditions. Thus, ballast resistors are not without value in MOSFET designs.
I agree that MOSFETs being paralleled should be matched. In practice this is not difficult, since most devices from the same tube tend to measure like peas in a pod.
Cheers,
Bob
Bob Cordell said:
I have matched several hundreds of power fets, most of them being IRFP9242 or IRF240 from IR. In my experience they don't match all that well from the same tube. Out of a tube of 25 there would be at least 2 or 3 that are pretty far off, too far off to be even considered used in parallel. The rest would be matchable within 2% VGS .
Magura
Magura said:
I have matched several hundreds of power fets, most of them being IRFP9242 or IRF240 from IR. In my experience they don't match all that well from the same tube. Out of a tube of 25 there would be at least 2 or 3 that are pretty far off, too far off to be even considered used in parallel. The rest would be matchable within 2% VGS .
Magura
That's pretty good matching. I did say "most". My experience has been similar.
Cheers,
Bob
Re: Heat transfer and thermal stability
Nice job! Beautiful yet functional.
I like the idea of using the top bar approach as well, but I've never been able to convince myself that the amount of heat it gets out is significant, since the top body of the transistor is plastic.
How much heat do you think is really going out the top? In other words, what do you think the value of Theta JT is, where T is the top bar?
Cheers,
Bob
Upupa Epops said:
Nice job! Beautiful yet functional.
I like the idea of using the top bar approach as well, but I've never been able to convince myself that the amount of heat it gets out is significant, since the top body of the transistor is plastic.
How much heat do you think is really going out the top? In other words, what do you think the value of Theta JT is, where T is the top bar?
Cheers,
Bob
Re: Re: Heat transfer and thermal stability
I routinely use the bar clamp method, not because of significant added heat dissipation capacity, but for the fact it is safer (insulation wise) and better distributes flange pressure to the heatsink.
Frequently it is simpler too, since most of the time you have pairs of closely spaced devices, so a single heatsink thread for a hefty screw in the middle, clamps both with the same force.
Rodolfo
Bob Cordell said:
I routinely use the bar clamp method, not because of significant added heat dissipation capacity, but for the fact it is safer (insulation wise) and better distributes flange pressure to the heatsink.
Frequently it is simpler too, since most of the time you have pairs of closely spaced devices, so a single heatsink thread for a hefty screw in the middle, clamps both with the same force.
Rodolfo
Workhorse said:
OK, but what does that have to do with SOA comparisons between high performance complementary BJT’s specifically designed for audio and the IRFP240?The SOA graph for that APT part sure looks impressive at first glance, but there are a few other practical considerations. Firstly, it’s temperature de-rating is over 4 watts per deg C. A typical BJT in the same package de-rates at about 1.4W/degC. Another problem is getting the heat out of the device. There is simply no way one of these devices could be heatsunk as easily and cost effectively as a few high power BJT’s simply connected in parallel to give an equivalent SOA.
Also, there many other device parameters besides SOA that dictates a device’s suitability for high power HiFi audio. Besides it’s high SOA, I don’t see too many parameters of that APT device that make it superior to the better BJT’s for audio use.
Cheers,
Glen
Bob Cordell said:
Bob,I do use a resistor [15 ohms ]in parallel with inductor..If low value of resistor is used then it effectively dampens the working of inductor and then placing the inductor there has of no significance ...The Inductor value which I use is 4uH[microHenry]...
My edge wound technique consists of inductor with 2"diameter with 6 turns..and thereby making the depth almost around less than 10mm....... DCR=0.005ohms
Cheers,
Kanwar
G.Kleinschmidt said:
The SOA graph for that APT part sure looks impressive at first glance, but there are a few other practical considerations. Firstly, it’s temperature de-rating is over 4 watts per deg C. A typical BJT in the same package de-rates at about 1.4W/degC. Another problem is getting the heat out of the device. There is simply no way one of these devices could be heatsunk as easily and cost effectively as a few high power BJT’s simply connected in parallel to give an equivalent SOA.
Also, there many other device parameters besides SOA that dictates a device’s suitability for high power HiFi audio. Besides it’s high SOA, I don’t see too many parameters of that APT device that make it superior to the better BJT’s for audio use.
Cheers,
Glen
Correct, BJTs are very easy to mount , easy to parallel....
But require a good current driving stage to drive them ...at least 3 EF stage are required to get a reasonable current gain in an amp ...whereas Mosfets require somewhat different topologies...easier to drive..requires less components....
As far SOA is concerned you ar right, but effective heatsink mounting with copper base could solve the problem in a much more efficient way and also there are other things to consider aswell....
Cheers'
Kanwar