Hello everyone !
I'm looking for some help with a problem that has been bugging me for a while.
I've built a half-bridge SMPS based on the sg3525 (which works at 35kHz) + tx4424 + GDT + IGBT. The end result should be a 14.4v and 200A DC power supply
When testing it failed after a matter of seconds. During the testing, the conduction time T-ON peaked at 47% out of a 50% maximum.
I suspected the dead-time was too little and reduced T-ON to 45%. Could a too low dead-time have caused the failure ? Or is there another cause ?
Here are some waveforms to help finding the cause of the failure
Scematic:
Video IGBT Blow at 14.4V /200A+
IGBTs blow - YouTube
Idle IGBT gate waveform
Idle primary waveform
Loud 14.4V / 50A igbt waveform
Loud 14.4V / 50A primary waveform
Please let me know what you think about the waveforms and what else I could do to improve them.
I'm looking for some help with a problem that has been bugging me for a while.
I've built a half-bridge SMPS based on the sg3525 (which works at 35kHz) + tx4424 + GDT + IGBT. The end result should be a 14.4v and 200A DC power supply
When testing it failed after a matter of seconds. During the testing, the conduction time T-ON peaked at 47% out of a 50% maximum.
I suspected the dead-time was too little and reduced T-ON to 45%. Could a too low dead-time have caused the failure ? Or is there another cause ?
Here are some waveforms to help finding the cause of the failure
Scematic:
An externally hosted image should be here but it was not working when we last tested it.
Video IGBT Blow at 14.4V /200A+
IGBTs blow - YouTube
Idle IGBT gate waveform
An externally hosted image should be here but it was not working when we last tested it.
Idle primary waveform
An externally hosted image should be here but it was not working when we last tested it.
Loud 14.4V / 50A igbt waveform
An externally hosted image should be here but it was not working when we last tested it.
Loud 14.4V / 50A primary waveform
An externally hosted image should be here but it was not working when we last tested it.
Please let me know what you think about the waveforms and what else I could do to improve them.
Last edited:
For the purpose of lov voltage and big current output the best topology is:
Phase Shifted Syncronous Rectified smps. This has the advantage of running in ZVS mode. So more sw frequency at lower sw losses.
With SG3525 you run it in forced switching mode witch is lossy and stresses the sw elements.
Take a look at LTC1922 or UUC38950.
Regards,
Savu
Phase Shifted Syncronous Rectified smps. This has the advantage of running in ZVS mode. So more sw frequency at lower sw losses.
With SG3525 you run it in forced switching mode witch is lossy and stresses the sw elements.
Take a look at LTC1922 or UUC38950.
Regards,
Savu
Last edited:
I ill be honest, at those power levels I would have been running MOSFET's. It would appear that the driver circuit you are using is for a MosFet so the change should be easy. For some reason I seem to remember that IGBT's need a current pulse to turn off completely. Maybe they have fixed things since I used them or maybe I am just mis-remembering.
Second item, can you show the primary side current waveform into the transformer? Also, the primary side transformer construction, Lp, turns ratio, and gap in the transformer would all be helpful. There is a possibility that the core may not be saturating.
Tony
Second item, can you show the primary side current waveform into the transformer? Also, the primary side transformer construction, Lp, turns ratio, and gap in the transformer would all be helpful. There is a possibility that the core may not be saturating.
Tony
Transformer ration 12: 2+2
Toroidal core R63 material K2006, Ae=300mm^2
datesheet: http://www.kaschke.de/ferrite/pdf/datenblaetter/Ringe2/R63-25.pdf
After I broke igbt's a test temp of ferrite core and it was cold.
I have an industrial smsp 14.4V 100A half bridge (tl494+totempole+GDT+ 47A-MOSFET) and i test it and this is rezult:
Idle (no loud) primary waveform
Loud 14.4V 50A primary waveform
I compared the results with my smps and I think are similar.
Ps I change my values of resistors(5R) and caps(1nF) on snubber whit 75R+1nF on my smps and this is result:
I wait your opinions!
Best regards,
Toroidal core R63 material K2006, Ae=300mm^2
datesheet: http://www.kaschke.de/ferrite/pdf/datenblaetter/Ringe2/R63-25.pdf
After I broke igbt's a test temp of ferrite core and it was cold.
I have an industrial smsp 14.4V 100A half bridge (tl494+totempole+GDT+ 47A-MOSFET) and i test it and this is rezult:
Idle (no loud) primary waveform
An externally hosted image should be here but it was not working when we last tested it.
Loud 14.4V 50A primary waveform
An externally hosted image should be here but it was not working when we last tested it.
I compared the results with my smps and I think are similar.
Ps I change my values of resistors(5R) and caps(1nF) on snubber whit 75R+1nF on my smps and this is result:
An externally hosted image should be here but it was not working when we last tested it.
I wait your opinions!
Best regards,
can you get a better shot of the voltage at the gate? during turn on specifically, it would appear your circuit is sufficient for turn off. however it appears it is oscillating at turn on. you may need to wind a stiffer gate transformer/
also, unless you cancel out the igbt diode with a schottky diode in series with the drain, that external diode is not going to do much to stop any failure mode related to the internal igbt diode.
also, unless you cancel out the igbt diode with a schottky diode in series with the drain, that external diode is not going to do much to stop any failure mode related to the internal igbt diode.
Man, try to use anything against trafo driver, with trafo driver you cannot adjust deadtime, and pulses are very distorted.
You can try this one, just mention to use ultrafast diode and good capacitor for bootstrapped supply (D4 and C4 in demo schematic on pdf), C4 use 22uF/25Vdc low esr, parralel with 0,1uF ceramic capacitor, as closest to pin 8 and 6, and 8,2-10 ohms gate resistor, without diode parralel.
The switch On-Off, will be fast enough.
http://www.onsemi.com/pub_link/Collateral/NCP5181-D.PDF
Good luck, trafo driver is rudimentary...
You can try this one, just mention to use ultrafast diode and good capacitor for bootstrapped supply (D4 and C4 in demo schematic on pdf), C4 use 22uF/25Vdc low esr, parralel with 0,1uF ceramic capacitor, as closest to pin 8 and 6, and 8,2-10 ohms gate resistor, without diode parralel.
The switch On-Off, will be fast enough.
http://www.onsemi.com/pub_link/Collateral/NCP5181-D.PDF
Good luck, trafo driver is rudimentary...
Last edited:
There is something wrong with your gate drive.
There is no path for the base current of the PNP's.
Also, you have 2KW....you cannot do this with a half-bridge unless you also have fans to cool the semiconductors.
Also, maybe you switch in the capacitive region in which case you get big switching losses.
Is it supposed to be an Asymetric resonant half-bridge?
There is no path for the base current of the PNP's.
Also, you have 2KW....you cannot do this with a half-bridge unless you also have fans to cool the semiconductors.
Also, maybe you switch in the capacitive region in which case you get big switching losses.
Is it supposed to be an Asymetric resonant half-bridge?
but we must remember switching losses also.
If you use half bridge, what size fets/igbts are you using, and how many of them....are you putting them in parallel?
Im sorry but at 2KW , you need full bridge.....half bridge only switches half of the bus...this isnt an audio supply, it will be on peak power continuously
If you use half bridge, what size fets/igbts are you using, and how many of them....are you putting them in parallel?
Im sorry but at 2KW , you need full bridge.....half bridge only switches half of the bus...this isnt an audio supply, it will be on peak power continuously
The question regarding gate signals is a key question.
Pretty helpful would be to see Uge and Uce of the lower switch in one screen shot at high load (max. level where you do not run into defects).
There is a general difficulty in these transformer gate drives.
During switching transition the capacitive coupling between both secondaries can cause an undesired driving signal to the switch which should remain off.
Especially at high load you get high dv/dt between both driving secondaries and already small coupling capacitances already can cause headache.
Some years ago this effect pushed me to redesign the gate drive transformer of a PSU for 1.3kW (1.3kW with a ON/OFF duty cycle of 1s/2s), the issue started at loads above 800W, so this would fit to your finding of defects at high loads.
Pretty helpful would be to see Uge and Uce of the lower switch in one screen shot at high load (max. level where you do not run into defects).
There is a general difficulty in these transformer gate drives.
During switching transition the capacitive coupling between both secondaries can cause an undesired driving signal to the switch which should remain off.
Especially at high load you get high dv/dt between both driving secondaries and already small coupling capacitances already can cause headache.
Some years ago this effect pushed me to redesign the gate drive transformer of a PSU for 1.3kW (1.3kW with a ON/OFF duty cycle of 1s/2s), the issue started at loads above 800W, so this would fit to your finding of defects at high loads.
choc:
you also see that with the bootstrap drivers.
It is a problem which exists, and industrial secrets exist to mitigate the problem you speak of.....many readers will have the secret answer which you seek, but will not tell.
all i can say is make the fet drain transition slow enough to make the effect less bad.
you also see that with the bootstrap drivers.
It is a problem which exists, and industrial secrets exist to mitigate the problem you speak of.....many readers will have the secret answer which you seek, but will not tell.
all i can say is make the fet drain transition slow enough to make the effect less bad.
@ eem2am
The issue with the capacitive coupling of the secondaries of the gate drive transformer does not exist in solutions with a boot strap driver.
If you use such a chip half bridge driver there is no gate drive transformer and consequently you will not struggle with its parasitics.
But of course there may remain other issues at high dv/dt, i.e. caused by the parasitics of the switches and/or layout.
P.S.
Was I seeking a secret answer?
I thought I was seeking for wave forms in order to remote debug a SMPS.
P.P.S.
You propose to reduce dv/dt.
Which detailed solution would you propose, except from brute force snubbering (undesired losses) or moving to quasi resonant (undesired massive redesign)?
P.P.P.S
Up to know we do not know the dv/dt - measurements are not detailed enough.
It's is just a first guess, that in the moment of turning OFF at high loads there will happen high dv/dt.
Also we do not know if there happens an issue in the gate drive at that (these) moment(s). Let's wait the detailed measurements.
The issue with the capacitive coupling of the secondaries of the gate drive transformer does not exist in solutions with a boot strap driver.
If you use such a chip half bridge driver there is no gate drive transformer and consequently you will not struggle with its parasitics.
But of course there may remain other issues at high dv/dt, i.e. caused by the parasitics of the switches and/or layout.
P.S.
Was I seeking a secret answer?
I thought I was seeking for wave forms in order to remote debug a SMPS.
P.P.S.
You propose to reduce dv/dt.
Which detailed solution would you propose, except from brute force snubbering (undesired losses) or moving to quasi resonant (undesired massive redesign)?
P.P.P.S
Up to know we do not know the dv/dt - measurements are not detailed enough.
It's is just a first guess, that in the moment of turning OFF at high loads there will happen high dv/dt.
Also we do not know if there happens an issue in the gate drive at that (these) moment(s). Let's wait the detailed measurements.
i nam wondering now , about your circuit because the problem of which you speak is not common when using gate drive transformers...have you got a pnp turn off circuit there?
Also, with a normal half bridge (non resonant) you cannot have both secondaries on the same core ....unless the both sides of the primary are grounded when both fets are to be off.......remember to watch for the potential disaster of light load when the series primary cap can discharge and saturate the gate drive transformer, allowing the secondary to be short, and then its series cap appears across the fet and turns it on when it should be off.
Also, with a normal half bridge (non resonant) you cannot have both secondaries on the same core ....unless the both sides of the primary are grounded when both fets are to be off.......remember to watch for the potential disaster of light load when the series primary cap can discharge and saturate the gate drive transformer, allowing the secondary to be short, and then its series cap appears across the fet and turns it on when it should be off.
Hi mgm2000ro,
from what I see on the schematic you gate driver has some problems:
you are trying to do a bipolar drive an then you clamp the negative part with the PNP and with the zener. I suggest the following modifications:
1) connect your transformer to your TC4424 using a series capacitor (around 1uF). This allows to be sure that no DC is stored in the transformer
2) remove you diodes and pnp assembly on the secondary side. This circuit will not work with bipolar drive.
3) connect the secondary side to the igbt only with a series resistor (gate resistor). If needed you can parallel this resistor with another resistor + diode to independently control the turn on and turn off.
4) reduce your 10kohm resistor on the secondary side to 1kohm or less, this helps damping the resonances of the gate drive transformer.
5) replace your gate zener with 2 back to back mounted 18v zeners. These are here to protect the gate and should normally never conduct. if your vdd is 15V select 18V zeners back to back.
Doing this you will have a bipolar drive for your IGBTs.
ciao
-marco
from what I see on the schematic you gate driver has some problems:
you are trying to do a bipolar drive an then you clamp the negative part with the PNP and with the zener. I suggest the following modifications:
1) connect your transformer to your TC4424 using a series capacitor (around 1uF). This allows to be sure that no DC is stored in the transformer
2) remove you diodes and pnp assembly on the secondary side. This circuit will not work with bipolar drive.
3) connect the secondary side to the igbt only with a series resistor (gate resistor). If needed you can parallel this resistor with another resistor + diode to independently control the turn on and turn off.
4) reduce your 10kohm resistor on the secondary side to 1kohm or less, this helps damping the resonances of the gate drive transformer.
5) replace your gate zener with 2 back to back mounted 18v zeners. These are here to protect the gate and should normally never conduct. if your vdd is 15V select 18V zeners back to back.
Doing this you will have a bipolar drive for your IGBTs.
ciao
-marco
OK... I had to go back and find my old notes... From what I can see there is no negative pulse to turn of the IGBT's correctly. As I noted before the scheme appears to be for a MOSFET and not a IGBT gate drive.
Please read the following paper. Look at page 26. You will see a method for the correct driving of the IGBT. the C1-Z1-D2 provides the negative transition to turn it off correctly.
http://www.ixyspower.com/images/tec... Topic/MOSFETs and IGBTs Drivers/IXAN0009.pdf
Ther are a few other methods. I've used a current sense transformer to do (because I was using it in a resonant topology and needed the current information anyway) but that is probably overkill for this.
Anyway, I hope that helps.
Tony
Please read the following paper. Look at page 26. You will see a method for the correct driving of the IGBT. the C1-Z1-D2 provides the negative transition to turn it off correctly.
http://www.ixyspower.com/images/tec... Topic/MOSFETs and IGBTs Drivers/IXAN0009.pdf
Ther are a few other methods. I've used a current sense transformer to do (because I was using it in a resonant topology and needed the current information anyway) but that is probably overkill for this.
Anyway, I hope that helps.
Tony
Such pnp can only catch the issues coming from the parasitic capacities of the power switches. It cannot overcome issues from capacities in the gate drive transformer.
And of course one can drive both switches from two isolated windings on the same core. Most commercial low&medium power solutions do this, because of cost reasons. There will not happen any saturation issue, because the 3525 drives with same pos. voltage time product as neg. voltage time product.
Effective drive transformer secondary load is even more symmetrical in a solution with two secondaries on one core compared vs. two separate cores. The primary cap only needs to catch minor imperfections.
Also the schematic at the beginning of this thread is showing such a solution.
If you choose seperate gate transformers for each switch, then the issue with capacitive coupling between both secondaries will not happen.
...looked again at the schematic and noticed that there is no capacitor between the drive transformer and the TC4424.
In perfect world such cap is not necessary, but in real world any driving imperfection (timing and symmetry of magnitudes as well) may cause a DC current through the primary of the drive transformer and consequently a pre magentization of the core. This could become an issue especially at high duty cycles.
If this is the issue should be visible by examining both gate drive signals at max ducty cycle. For this examination you may power the upper collector not from 300V, but from a 15V...30V lab supply.
The advantage of this is set up is current limitation and also the sg3525 will automatically regulate to max duty cycle, because the output voltage will remain far below the target value.
In perfect world such cap is not necessary, but in real world any driving imperfection (timing and symmetry of magnitudes as well) may cause a DC current through the primary of the drive transformer and consequently a pre magentization of the core. This could become an issue especially at high duty cycles.
If this is the issue should be visible by examining both gate drive signals at max ducty cycle. For this examination you may power the upper collector not from 300V, but from a 15V...30V lab supply.
The advantage of this is set up is current limitation and also the sg3525 will automatically regulate to max duty cycle, because the output voltage will remain far below the target value.
- Status
- This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.