Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter

I know you are not asking me, but I have kind of a setup like this "built-in" in my DAC. I have both a WaveIO and a RPI3 with I2S output which goes through an FiFoPi with reclock-pi to the I2S input my DDDAC1794. I use a relay "switch" to select the one or the other by IR-Remote.

I have tried what I believe you want to know. Just for fun, I connected the USB output of the RPI3 to the WaveIO. This means that the music signal is available from both I2S outputs. Hence, I could A-B switch (remote control) between RPI-I2S-FiFoPi and RPI-USB-WAveIO-I2s-FiFoPi while listening. I did the test "blind" - Just eyes closed and pushing the IR-Remote control many times and then A-B so no clue what input played at the time. I could not really tell a difference.

sorry for interfering ;)

Doede
 
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Just remember, the higher the clock, the more it is both susceptible to and a generator of noise / interference.

If you look at pretty much any digital high speed serial device these days, they use a low speed clock and divide it down to get higher speed ones. The reason is that generating those higher frequency clocks externally... far away from where they are going to be used... is... non-optimal. Generate a highly accurate base clock of some lower MHz and then divide it down much, much closer to the hardware which will use it where it will suffer much less interference. Additionally having high powered high Mhz xtals on a PCB will have RF emissions issues.

A prime example would be capacitance effects. If you have a 24Mhz clock and you measure a 3ns rise time and see some sinusoidal rounding at the top. When you convert it to a 96Mhz clock, all other things remaining equal, you STILL have 3ns rise time and even more sinusoidal rounding as that is governed by the capacitance of the entire clock circuit. The overshoot/undershoot/ringing (which will slowly wear IC protection circuits out) is governed by the inductance of the circuit and won't get better, might get worse, or even cause LC resonance and your clock go completely nuts.. or just die.

So a higher clock can actually result in a worse timing performance and will almost certainly suffer more interference and cause headaches.

Good scope will serve you well.
 
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I've been trying to find ways of explaining the master clock, because I believe there is a lot of miss-conceptions surrounding it.

For devices which require a master clock, they are using that clock to drive the IC I2S circuitry.

In the same way an old ZX81 would had a 3.1Mhz xtal and every single operation, no mater how small, is ALWAYS done on a clock pulse. That's how it all works. Without that it's not a digital circuit, really. (debate me).

Going back 30 or 40 years audio clocks were a big deal. ICs ran at single or double digit mega-hertz. Today, not so much. It is highly likely in the 1970s and 1980s that a master IC clock of 24.576Mhz was unthinkable in a digital circuit and it's very likely that none of the processing or other ICs would run at that frequency. So it if it was important for just the digital audio I2S hardware to run at a much higher rate... you have to send it with the signal.

There are of course devices which do not require or provide a master clock. How can this be? Well, they just choose not to run the I2S digital circuitry from an external clock. They run it on their own internal clock.

As mentioned though, just because your ADC/DAC can run it's I2S peripheral at 24.576Mhz says nothing about 98Mhz.

EDIT: Of course picking a clock frequency that allows all the various multiples to be derived easily and accuately with clock dividers does make things a lot easier.
 
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:) Sorry. Been spending a little bit too much time with I2S low levels.

I keep waking up at night thinking about clock lines, data lines, AND gates and shift registers with flip flop state machines and ladder DACs.... no I'm joking I don't, not when I'm sleeping anyway :) I'm just wondering if you could create an I2S DAC with nothing more than bunch of HC74 TTL ICs and some passives.
 
While I'm waiting for some parts to arrive for my next projects, I'm re-visiting Ian's PurePi battery and super cap kit I bought a few months back. This is a fascinating little PSU. Clearly it was designed specifically for the RPi. Ian has once again shown us his genius. Powering through the GPIO with the tiny spring contacts works superbly. :) Focusing on DAC's power supply can (and will) make a difference in the sonics. This little board allows for all the voltages you will need to get a simple DAC/Streamer up and running.

I took an 'older' DAC hat I had - the MamboBerry LS - and put it atop the RPi. I then added a little 5" LCD and configured ropieeeXL (my roon bridge) to provide a rudimentary means of simple transport and artist/album art to the mix. I'm still surprised and amazed at the quality of sound coming from this combo. Keep in mind, the MamboBerry is like 5 yrs old, but used the ES9023P, 24-bit DAC. Anyway, thought I'd share some pictures of it. Now all I need is to dream up a nice looking enclosure to show-case it. :)
 

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@drone

That would be up to your application. If your DAC can take 90/98 then going with it. I got some good result with 90/98 MHz. I'll post the update soon.
BTW, I ordered some true SC-CUT 45/49 crystals. I'm working on designing some really great low phase noise clocks that can be directly installed to FifoPi Q7.

Ian
Thx Ian,

using your dual mono dac atm. Will try with my Buffalo 9038pro and hdmi pro once I get it.
think booth can handle 90/98 MHz clocks?
so will try these

regards
Branko
 
Thanks God, "ignore" button works...
Some people value understanding of "why" and "how", rather than just parrot buy.

If you don't understand what the master clock does in the first place...

It's like people putting snow chains on the front wheels of their car because that's what everyone else in the street did. Only their car is rear wheel drive.
 
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@drone

That would be up to your application. If your DAC can take 90/98 then going with it. I got some good result with 90/98 MHz. I'll post the update soon.
BTW, I ordered some true SC-CUT 45/49 crystals. I'm working on designing some really great low phase noise clocks that can be directly installed to FifoPi Q7.

Ian
Ian, did you find out if it is possible to buy ready-made generators from them? (minimum quantity, price, terms, etc.)

And I ordered only resonators to make it not much worse but much cheaper?
 
I've been trying to find ways of explaining the master clock, because I believe there is a lot of miss-conceptions surrounding it.

For devices which require a master clock, they are using that clock to drive the IC I2S circuitry.

In the same way an old ZX81 would had a 3.1Mhz xtal and every single operation, no mater how small, is ALWAYS done on a clock pulse. That's how it all works. Without that it's not a digital circuit, really. (debate me).

Going back 30 or 40 years audio clocks were a big deal. ICs ran at single or double digit mega-hertz. Today, not so much. It is highly likely in the 1970s and 1980s that a master IC clock of 24.576Mhz was unthinkable in a digital circuit and it's very likely that none of the processing or other ICs would run at that frequency. So it if it was important for just the digital audio I2S hardware to run at a much higher rate... you have to send it with the signal.

There are of course devices which do not require or provide a master clock. How can this be? Well, they just choose not to run the I2S digital circuitry from an external clock. They run it on their own internal clock.

As mentioned though, just because your ADC/DAC can run it's I2S peripheral at 24.576Mhz says nothing about 98Mhz.

EDIT: Of course picking a clock frequency that allows all the various multiples to be derived easily and accuately with clock dividers does make things a lot easier.

@paulca

To select higher or lower MCLK frequencies is a very good question, But it would be a long story.

Different DACs take clock frequencies differently. R-2R DACs don't use the MCLK directly, they just use up to 384KHz SCK which is generated by MCLK. But ESS D-S DACs can take MCLK higher than 100MHz. D-S DACs may also divide the MCLK down to lower frequency internally to match the Fs. But no matter what, we will need at least one MCLK at a time in the system. Basically lower phase noise or less jitter MCLK result in better SN thus the sound quality will be improved. So it's all about the jitter and phase noise.

To select higher MCLK or Lower MCLK, it's the question.

Based on Leeson's equation, Doubling the MCLK frequency results in 6dB Phase Noise degradation. While, each time dividing the frequency by 2 it will lead to 6dB phase noise improvement. (This is the principle, in the real world, there will be more consideration)
https://en.wikipedia.org/wiki/Leeson's_equation

So, if you have two AT-CUT clocks at similar phase noise levels, the higher frequency clock will be benefit from this principle.
But if you have a lower frequency OCXO or SC-CUT clock with really great close-in phase noise performance, and if it is always better than the AT-CUT clock no matter how many times to divide, then the OCXO would be the better option.
However, some OCXOs have very good close-in phase noise numbers, but the noise floor could be not that great, in this case, compromise has to be made when selecting the MCLK frequencies.

I recently did some real listening tests on my Spring3 R-2R with FifoPiQ7/HdmiPiPro and different clocks. The results are very interesting. I'll post more updates with details.

Good weekend,
Ian
 

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thanks @paulca for ssharing this very interisting approach. It leads to thinking about this subject, which is always a good thing (we would have know for long if audio matters where settled in stone:)).
I guess I took the easiest path chosing 90/98 accusilicon clock, but after reading tones of pages here, it seems the most versatile yet without sacrifice to sound quality.
I know by heart my hifi system now, and now that my mytek brooklyn bridge is on sell mode, I got my list of songs ready when my dac/streamer/roon endpoint will be ready.
 
I finally finished my personal D11 Dac, based on UCpure.
I struggled when I started a few years ago with the lack of complete examples of builds and decided to share my projects. May not be perfect but hope it helps someone starting out.
Detailed build on my YouTube Chanel.
Happy Holidays to all
Gaby

This is an awesome build, Gaby. Love how you putting it together.
 
I know you are not asking me, but I have kind of a setup like this "built-in" in my DAC. I have both a WaveIO and a RPI3 with I2S output which goes through an FiFoPi with reclock-pi to the I2S input my DDDAC1794. I use a relay "switch" to select the one or the other by IR-Remote.

I have tried what I believe you want to know. Just for fun, I connected the USB output of the RPI3 to the WaveIO. This means that the music signal is available from both I2S outputs. Hence, I could A-B switch (remote control) between RPI-I2S-FiFoPi and RPI-USB-WAveIO-I2s-FiFoPi while listening. I did the test "blind" - Just eyes closed and pushing the IR-Remote control many times and then A-B so no clue what input played at the time. I could not really tell a difference.

sorry for interfering ;)

Doede
Than I guess you did not use the drixo clocks on the fifopi when testing?
 
@paulca

To select higher or lower MCLK frequencies is a very good question, But it would be a long story.

Different DACs take clock frequencies differently. R-2R DACs don't use the MCLK directly, they just use up to 384KHz SCK which is generated by MCLK. But ESS D-S DACs can take MCLK higher than 100MHz. D-S DACs may also divide the MCLK down to lower frequency internally to match the Fs. But no matter what, we will need at least one MCLK at a time in the system. Basically lower phase noise or less jitter MCLK result in better SN thus the sound quality will be improved. So it's all about the jitter and phase noise.

To select higher MCLK or Lower MCLK, it's the question.

Based on Leeson's equation, Doubling the MCLK frequency results in 6dB Phase Noise degradation. While, each time dividing the frequency by 2 it will lead to 6dB phase noise improvement. (This is the principle, in the real world, there will be more consideration)
https://en.wikipedia.org/wiki/Leeson's_equation

So, if you have two AT-CUT clocks at similar phase noise levels, the higher frequency clock will be benefit from this principle.
But if you have a lower frequency OCXO or SC-CUT clock with really great close-in phase noise performance, and if it is always better than the AT-CUT clock no matter how many times to divide, then the OCXO would be the better option.
However, some OCXOs have very good close-in phase noise numbers, but the noise floor could be not that great, in this case, compromise has to be made when selecting the MCLK frequencies.

I recently did some real listening tests on my Spring3 R-2R with FifoPiQ7/HdmiPiPro and different clocks. The results are very interesting. I'll post more updates with details.

Good weekend,
Ian
Ian,

Do please elaborate on real listening tests with different clocks.
 
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