that is, if the majority of dac noise is 'systematic'. Random noise generated by the dac and added circuitry (eg logic) is actually doubled.
Phase shift is probably more detrimental to the sound than roll-off, no?
I would suggest that the biggest noise component is not random but due to the internal switching so the overall result is less noise.
As one dac is used per channel, each pair of dac outputs should have (theoretically) the same amplitude and polarity of noise which will therefore cancel in the transformer.
The HCT14 is not a buffer. If you need additional fanout, use a low-skew clock driver designed for that purpose. If you need drive for a long cable, use a differential clock driver designed for that purpose.
Consider the additional noise added by unnecessary gates switching at the same time. When the source of the sample clock changes state, a spike of noise and ground bounce is injected into the circuit. Moments later, before the noise has had a chance to dissipate, the first inverter receives the changing clock edge and inverts it. The Schmidt trigger references Vcc and ground to determine the trigger points but the reference is polluted with noise. Then, as it is changing state, the first inverter injects additional noise and ground bounce into the circuit, which, in turn, degrades the operation of the second inverter. Your buffer has degraded the clock signal and increased jitter. A single pico-gate is sufficient to invert one data line with minimal impact on the rest of the circuit.
Also, inverting the data to one dac is insufficient to create a proper differential output. You must negate each sample value otherwise you will add a DC offset. Transformers, like the 9545, work best when there is no DC offset.
I'm getting flashbacks from this thread. DC yes, but not a lot (lsb). Allthough it goes wrong at one of the end values iirc. All discussed (a lot) before..
As the currents return to +5, it makes sense to use a diff setup. In theory the current going through +5 is then 0 (assuming a perfect dac), the changing audio currents that is. The offset current of the 1541 doubles, but that's only DC.
If you want to do the inverting properly, the best way is a dig. filter and use the 1541 in another mode (not i2s). In that way you can correctly invert the feed to one channel. or a lot of logic in a cpld or fgpa.
As the currents return to +5, it makes sense to use a diff setup. In theory the current going through +5 is then 0 (assuming a perfect dac), the changing audio currents that is. The offset current of the 1541 doubles, but that's only DC.
If you want to do the inverting properly, the best way is a dig. filter and use the 1541 in another mode (not i2s). In that way you can correctly invert the feed to one channel. or a lot of logic in a cpld or fgpa.
In case of the tda1541 one LSB would result in an offset current of 61nA I would think most any signal transformer could tolerate that.
2's complement inversion falls apart for the most negative number so the logic would also have to handle that case. Besides if the data is encoded with "real" or absolute zero at 0.5 lsb then its actually correct to only invert the data.
In any case I'm not losing any sleep over this.
2's complement inversion falls apart for the most negative number so the logic would also have to handle that case. Besides if the data is encoded with "real" or absolute zero at 0.5 lsb then its actually correct to only invert the data.
In any case I'm not losing any sleep over this.
I'm adopting Tazzz's suggestion of using a 1541 per channel and therefore in simultaneous mode. The data will be split into left and right for feeding to each 1541 - probably using hc02s like Audio Note and the AD1865.
From post 3409
I tested this dual-mono mode recently, using a simple I2S encoder that converts L/R to L/L for chip #1 and R/R for chip #2. Both chips receive same BCK and WS signals, only the DATA signal for each chip differs. I didn't use balanced mode so possible "issues" with inverting DATA wouldn't occur.
From post 3409..
I tested this dual-mono mode recently, using a simple I2S encoder that converts L/R to L/L for chip #1 and R/R for chip #2. Both chips receive same BCK and WS signals, only the DATA signal for each chip differs. I didn't use balanced mode so possible "issues" with inverting DATA wouldn't occur.
Interesting experiments ahead to see just what happens (audibly) with inverting the data.
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EXPERIMENT WITH I/V TRANSFORMERS
I couldn't wait to finish the dual differential design so decided to experiemtn with the I/V transformers.
I disconnected the existing opamp & filter components from an old Philips Cd471 and soldered an LC Tee* filter loaded by 150R to the 1541 outputs.
The Sowter transformer primaries were paralled and connected across the 150r load and the secondaries series connected and fed directly to the amps aux input.
*2x 1mh in series and 100n to ground from the midpoint (online calculators with F-3 at 16khz, Z = 100r produced 2 x 1mh and 200n which I did try)
Without the filter there were audible artifacts as expected, but vastly reduced by the filter without major loss of hf (to my old ears!) and certainly listenable to and not a fet, tube, opamp or transistor in sight!
I couldn't wait to finish the dual differential design so decided to experiemtn with the I/V transformers.
I disconnected the existing opamp & filter components from an old Philips Cd471 and soldered an LC Tee* filter loaded by 150R to the 1541 outputs.
The Sowter transformer primaries were paralled and connected across the 150r load and the secondaries series connected and fed directly to the amps aux input.
*2x 1mh in series and 100n to ground from the midpoint (online calculators with F-3 at 16khz, Z = 100r produced 2 x 1mh and 200n which I did try)
Without the filter there were audible artifacts as expected, but vastly reduced by the filter without major loss of hf (to my old ears!) and certainly listenable to and not a fet, tube, opamp or transistor in sight!
Here are two measurement on the output of the dac while its running a 1Khz sine at -60dbFS The measurement is first taken with the negative output shorted to ground at the output of the dac you can see it below:
An externally hosted image should be here but it was not working when we last tested it.
Here is the same measurement again only this time its measured differentially.
An externally hosted image should be here but it was not working when we last tested it.
I am constructing DAC as is under discussion in this tread - differential TDA1541, with splitting conventional I2S streams to separate L and R streams, and using Sowter 9545 to handle differential outputs.
Concerning one LSB DC offset between outputs of same TDA1541 - I'm pretty sure that Sowter 9545 will "handle" 60nA DC without any saturation
But there is an easy option to null this error DC offset by means of 2mA injection circuit (regulated CCS), if you use such
. You just need to set 0 VDC (to AGND) then TDA1541 receives digital zero on one of output. Do the same with second output of same TDA1541. After that connect multimetter between outputs and set 0VDC by tuning resistor value on channel with inverted data. Finally connect 9545 between both outputs. Concerning reflected input impedance of preamplifier - I'm going to load secondary of 9545 with proper resistor and use valve stage with amplification and buffering. I'm gonna use an Aikido stage, which is actually SRPP with following cathode follower, modified by John Broskie to have greater PSRR. Buffer also solves worst problem of SRPP - influence of load impedance.
Because of signal pass through transformer and valve stage I think there is no any need for special RC filter between TDA1541 output and 9545 primary. Here is only need to play with R value on valve input, using grid's Miller capacitance to form low pass filter.
Concerning one LSB DC offset between outputs of same TDA1541 - I'm pretty sure that Sowter 9545 will "handle" 60nA DC without any saturation
But there is an easy option to null this error DC offset by means of 2mA injection circuit (regulated CCS), if you use such
Concerning reflected input impedance of preamplifier - I'm going to load secondary of 9545 with proper resistor and use valve stage with amplification and buffering. I'm gonna use an Aikido stage, which is actually SRPP with following cathode follower, modified by John Broskie to have greater PSRR. Buffer also solves worst problem of SRPP - influence of load impedance.
Because of signal pass through transformer and valve stage I think there is no any need for special RC filter between TDA1541 output and 9545 primary. Here is only need to play with R value on valve input, using grid's Miller capacitance to form low pass filter.
I did think about nulling out the offset but the 60na isn't going to be an issue for the 9545s and my 57year old hearing apparatus won't detect lsb errors anyway (and will be filtering out regrettably, pretty much everything over 10-12kHz as well!)
When I was using the dual dacs in parallel mode, I did have a LCL T filter between dacs & tx but have no filters in circuit for the differential testing.
I will try removing the dac i/v resistor and using a secondary load.
My Quad 34 preamp's tape input is sensitive enough (100mv) for no additional preamp to be needed.
Have you considered the requirement of the dac when used in simultaneous mode*, to have offset binary data, not twos complement?
* one dac per channel receiving data and inverted data on pins 3 and 4 and pin 26 to -5v.
Ianj
I would not recommend to remove i/v resistor if you load outputs by primary section of 9545 in paralel of i/v resistors without 2mA DC injection.
Here is still risk of magnetizing 9545's core on startup of DAC, except you have some circuitry which will "reset" TDA1541 (loading it with digital zeros).
Or you should switch on DAC with data stream (I2S, SPDIF or whatever) already on input.
No, I use time multiplexed I2S mode, as I'm pretty sure that less logic chips introduces less jitter issues. Schematic provided by Pedja Rogic is simple enough to split the I2S stream.
If I would decide to use TDA1541 in simultaneous mode, I would take as transport any Philips or Marantz CD player with TDA1540 chips, make SAA7000 16 bit instead of 14bit mode and wire out clock, LE and both data streams via RJ45 socket to DAC with double TDA1541, ready to go in simultaneous mode
I would not recommend to remove i/v resistor if you load outputs by primary section of 9545 in paralel of i/v resistors without 2mA DC injection.
Here is still risk of magnetizing 9545's core on startup of DAC, except you have some circuitry which will "reset" TDA1541 (loading it with digital zeros).
Or you should switch on DAC with data stream (I2S, SPDIF or whatever) already on input.
No, I use time multiplexed I2S mode, as I'm pretty sure that less logic chips introduces less jitter issues. Schematic provided by Pedja Rogic is simple enough to split the I2S stream.
If I would decide to use TDA1541 in simultaneous mode, I would take as transport any Philips or Marantz CD player with TDA1540 chips, make SAA7000 16 bit instead of 14bit mode and wire out clock, LE and both data streams via RJ45 socket to DAC with double TDA1541, ready to go in simultaneous mode
Thanks for the info. I will take your advice and retain the I/V resistors and use the 9545 as step up transformers / impedance converters, with no secondary resistor, just 100k impedance of the preamp, as I'm doing now.
I agree that the extra logic needed to use one dac per channel (simultaneous mode) will cancel out any advantage compared to using I2S mode - ie one dac for true and one for inverted data.
This method is working and sounding good, if not a big advance on parallel dacs but I need to update one of the Quad 405-2s I won on Ebay. The older one I am using whilst the other is being updated is not as sweet sounding and masking some of the improvements. The 25year electrolytics are mumified by now!
I have started (on a conceptual level) to sketch the features of the next dac I will build. Emphasis is on the digital section as I want to be able to reuse most parts for an Arda AT1401 dac should it become available.
The main features are:
Dual differential (2xTDA1541)
Dual Spdif inputs
44.1-192k input sample rate range.
Two clock modes: Either internal DPLL controlled master clock or wclk slaving (signal source is slave)
I invite you to have a look at the conceptual diagram and give your comments.
The main features are:
Dual differential (2xTDA1541)
Dual Spdif inputs
44.1-192k input sample rate range.
Two clock modes: Either internal DPLL controlled master clock or wclk slaving (signal source is slave)
I invite you to have a look at the conceptual diagram and give your comments.
Attachments
Quite complex peripheral circuits I must say... if you are building this for your own use, I would suggest to limit options and make upfront decisions on what you want on:
-DEM rate
-Why would one need i2c?
-2 spdif receivers?
-12Mhz clock?
-192khz/16bits????
-Filtering?
Less is usually more...
-DEM rate
-Why would one need i2c?
-2 spdif receivers?
-12Mhz clock?
-192khz/16bits????
-Filtering?
Less is usually more...
To use 1 dac per channel (simultaneous mode), ie true and inverted data in pins 3 and 4, you need offset binary and I think a modified frame pluse to latch the data after the 16th bit has been received.
What's our thinking on this?
I am not keen on adding even more, possibly jitter inducing logic with shift registers etc required to use the dacs in time multiplexed mode, though I did consider an exor gate to invert only the msb of the L & R data streams to provide offset binary.
But I am currently using the simplest option with one dac for true and one for inverted data. It does at least have the advantage of needing no more than 1 inverter. Whether this is audibly superior to one dac per channel wth its added logic requirement remains to be seen (or heard).
After I/V conversion with ECDesigns single 2Sk170 design, the Sowter transformer is connected between the true and inverted fet outputs. Thus avoiding a ground connection and therefore no dc flows through the transformer primary. (will be testing this weekend)
Ian
The features I mention are pretty much those I miss from the DAC on page one on this thread.
I intend to use that dac as a testbed for some of the new blocks before I integrate everything together on a nice multilayer (>=4) pcb.
I have previously used a 64bit deep shift register to split the data into left and right this works fine. Reducing the i2s frames to 32bit it would be possible to reduce the length of shift register needed by half aswell.
I'm not particularly worried of 32 or so flip flips in a qfn package toggling on multilayer pcb.
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