Hi All,
So continuing my search for a BF862 version I came across this amazing article by Andrew Russell at Hifisonix.com
http://hifisonix.com/wordpress/wp-content/uploads/2015/01/UBx.pdf
I have also followed this thread but has left with more questions than answers.
http://www.diyaudio.com/forums/pass-labs/140488-b1-turbo-chip.html
I liked the idea of Patrick (EUVL) so trying to implement a dual BF862 BUFFER stage with even lower output impedance (20Ohm).
Andrew Russel explains how he select the Value of 49.2 ohm for source resistors. He however does not use source resistor for upper JFETS.
Dennis Feucht in his article describes (attached) how both Rsl and Rsu compensate for voltage drop.
Patrick however uses a source resistor value of 1.5Ohm. He explains it in post number #6.
What I am trying to figure out is why the source resistor value are different?
Will addition of trimpot to fine tune source resistor value eliminate the need for matching jfets?
So continuing my search for a BF862 version I came across this amazing article by Andrew Russell at Hifisonix.com
http://hifisonix.com/wordpress/wp-content/uploads/2015/01/UBx.pdf
I have also followed this thread but has left with more questions than answers.
http://www.diyaudio.com/forums/pass-labs/140488-b1-turbo-chip.html
I liked the idea of Patrick (EUVL) so trying to implement a dual BF862 BUFFER stage with even lower output impedance (20Ohm).
Andrew Russel explains how he select the Value of 49.2 ohm for source resistors. He however does not use source resistor for upper JFETS.
Dennis Feucht in his article describes (attached) how both Rsl and Rsu compensate for voltage drop.
Patrick however uses a source resistor value of 1.5Ohm. He explains it in post number #6.
What I am trying to figure out is why the source resistor value are different?
Will addition of trimpot to fine tune source resistor value eliminate the need for matching jfets?
Thanks guys. If anyone can explain why the two designs have different source resistors? Obviously Andrew Russel is running the devices at a low IDss and no where in article he mentions about IDss matching.
Patrick also mentioned he did not closely match and result he published indicate a 2.5mV offset.
Both these guys did not mention abou using a trim pot to accurately change the IDss but Andrew Russel mentioned it.
I guess if I don't use upper source resistors it will change Vd? But that also means if I use a trim pots I can accurately dial in Vd, right? If I am using a 47 ohm source resistors that also means the devices are not running at IDss but at a current specified by me.
Patrick also mentioned he did not closely match and result he published indicate a 2.5mV offset.
Both these guys did not mention abou using a trim pot to accurately change the IDss but Andrew Russel mentioned it.
I guess if I don't use upper source resistors it will change Vd? But that also means if I use a trim pots I can accurately dial in Vd, right? If I am using a 47 ohm source resistors that also means the devices are not running at IDss but at a current specified by me.
Ok,for making it easy here are the pictures.
Please read page 8 from the pdf in the link where Andrew russel explains how he designed the circuit.But the picture he has in document is different in Rs value from the description. Marked in Red.
http://hifisonix.com/wordpress/wp-content/uploads/2015/01/UBx.pdf
This is what Patrick explains his Rs values
The degeneration resistor Rs can be calculated as :
Rs = ( Idss – Id ) / ( Id . Yfs )
With 2x matched BF862 in parallel, and assuming 20mA total bias current,
Idss per FET (mA) ___ Rs (ohm)
11 ___ 1
12 ___ 2.2
13 ___ 3.3
14 ___ 4.7
15 ___ 5.1
16 ___ 6.8
17 ___ 8.2
18 ___ 9.1
19 ___ 10
20 ___ 11
Please read page 8 from the pdf in the link where Andrew russel explains how he designed the circuit.But the picture he has in document is different in Rs value from the description. Marked in Red.
http://hifisonix.com/wordpress/wp-content/uploads/2015/01/UBx.pdf
This is what Patrick explains his Rs values
The degeneration resistor Rs can be calculated as :
Rs = ( Idss – Id ) / ( Id . Yfs )
With 2x matched BF862 in parallel, and assuming 20mA total bias current,
Idss per FET (mA) ___ Rs (ohm)
11 ___ 1
12 ___ 2.2
13 ___ 3.3
14 ___ 4.7
15 ___ 5.1
16 ___ 6.8
17 ___ 8.2
18 ___ 9.1
19 ___ 10
20 ___ 11
Attachments
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Please do explain why?
I do like Patrick's design but could not figure out how the resistors change that much.
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Because Andrew read WAY TOO many text books, while Patrick just read TOO many text books.
Picodumb that is not helping me. I do not know both of them.
My question remains unanswered. How do you calculate the Rs value. From Andrew Russel'S ARTICLE.
JFET Operating Conditions.
For our application, the maximum undistorted load current is 5V pk into 10k Ω – so 2mA. We also want to make sure that the maximum source current out of Q4 remains below the minimum Idss value of 10mA. If we then allow say 1mA to spare, this tells us the current source load needs to be somewhat below 7mA. Looking at the red line in the LHS panel, it can be seen that if we do not want to individually select the JFET’s (i.e. just order them and place them on the board with a guaranteed good result) we have to ensure that at the upper Id extreme (top curve in LHS panel), we do not exceed the Idss 10mA figure at 5V pk. Below that, we are ok, but have to accept that at >5V pk into 10k, there [FONT=Calibri,Calibri][FONT=Calibri,Calibri]may [/FONT][/FONT]be some additional distortion. 2Vpk will drive just about any power amplifier you can think of to full power and at that level, the distortion on this buffer is extremely low. We should conclude therefore that this is a sensible design tradeoff. Of course, you can always adjust the value of R1 and R14 individually to make sure that the current source is set to exactly 6.5mA – the target set above. With this information, its easy to now calculate the correct value of R1 and R14 from the typical curve from Vgs/Id and we then get 0.32 V/6.5 mA = 49.2 Ω – use 47 Ω standard value.
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Less degeneration, lower output impedance, plus no output cap, is clearly better.
Patrick offers calculation so as to achieve exactly 20mA regardless of Idss figure. Higher Idss parts require greater degeneration to achieve 10mA per device. That is, Vgs is driven more negative by increasing the source resistance, which reduces Id.
20mA is not a magic number so you don't need exactly 20mA.
If Vds is kept to 12V anything between 20mA and 30mA would be fine for a parallel pair.
All you need is reasonably matching parts maybe 5 Ohms source resistors and a 20 turn 10 Ohm trimpot on the current source to get 0V dc Offset.
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There is going to be a cap at output if I am using it as a pre amp as it is not DC coupled.
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