It will give you about 88C of junction temperature which is safe and far away from maximum (175).
5 deg difference between fets and rest of hsink is good
regarding overal temp - it's important that lower and upper plate have enough holes , so inner parts aren't scorched
anyway - just remember MF A1 and A100 - they just couldn't live that long as majority of them lived .....
Are you kidding me? Gustav Kirchhoff was one of electrical PAPAs like Georg Ohm.
Gustav Kirchhoff - Wikipedia, the free encyclopedia
Kirchhoff's circuit laws - Wikipedia, the free encyclopedia
thank you
would you measure Vds of pair
I like to know the exact practical value of dissipation of each FET because I would like to try If possible to higher bias on MF35-151.5
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I'm going to reiterate what I said earlier about the current limiting aspects of the Aleph J. Below is a paragraph from NPs F5 article.
(Understanding the limiting circuit is easy. Q5 and Q6 look at the voltages across the R11 and R12, and will start to conduct when their Base to Emitter voltage exceeds .4 volts or so. At .4 volts Q5 and Q6 draw off enough drive current from Q1 and Q2 to start creating measured distortion, and hard limiting occurs when the voltage driving Q5 or Q6 is increased to .6 volts.)
For all you self proclaimed experts, go argue with The Master. Sometimes trying to be helpful around here just isn't worth the abuse. And I studied Kirkhoff's law when he was still alive.
(Understanding the limiting circuit is easy. Q5 and Q6 look at the voltages across the R11 and R12, and will start to conduct when their Base to Emitter voltage exceeds .4 volts or so. At .4 volts Q5 and Q6 draw off enough drive current from Q1 and Q2 to start creating measured distortion, and hard limiting occurs when the voltage driving Q5 or Q6 is increased to .6 volts.)
For all you self proclaimed experts, go argue with The Master. Sometimes trying to be helpful around here just isn't worth the abuse. And I studied Kirkhoff's law when he was still alive.
Bill,
if you calculate the voltage drop across limiting transistors in Alpeh J and F5 at idle you will get about 0.39V in both. I just wanted to say that such schematics can be mathematically calculated and we do not need to guess if some resistors have too high/low values.
It would be nice if Mr. Pass comments it.
PS. Sorry, I did not mean to abuse anyone.
if you calculate the voltage drop across limiting transistors in Alpeh J and F5 at idle you will get about 0.39V in both. I just wanted to say that such schematics can be mathematically calculated and we do not need to guess if some resistors have too high/low values.
It would be nice if Mr. Pass comments it.
PS. Sorry, I did not mean to abuse anyone.
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Gustav Robert Kirchhoff (12 March 1824*– 17 October 1887)
Bill you met ihm really?
Maybe it was his grandson.
That's kind of a red herring. In the stock J I believe the AC current gain is set up around 42% so you will start clipping asymetrically before you get to max current in the signal fets. You can use double the bias as your threshhold and go another bit for safe measure. After all, you sure don't ever want to hear it working, as I did.
There's no a relationship. Asymmetrical clipping occurs in the case when the positive swing is restricted by the current source but negative swing is restricted by the negative power supply voltage if the current limiting circuit is not implemented. In case of correctly implemented current limiting for negative swing they both are equal. Aleph J is design to have both swings symmetrical in term of output current. In F5 it's achieved by a symmetry in the circuit itself.
Yes, you can adjust R14 to get precise symmetry in clipping dependently of the component used.
