http://www.diyaudio.com/forums/digi...ad-new-take-classic-pass-labs-d1-ess-dac.html is the build thread, with BOM
How did nobody catch this??????
Hi Guys,
It has been a long time since there were any updates on this page, but I've recently taken this design out and dusted it off to take a fresh look at how I can reduce the power consumption without reducing the performance.
I was running some simulations when I had a bit of a "Aha!" moment.
Can anyone here take any guesses? It's painfully obvious as soon as you see it.
Take a look at the negative supply, and ask yourself, "What is this doing for us?".
The answer is... nothing, except dissipating 50% of the current power dissipation.
The voltage at the source of each fet is roughly 1.75VDC, and since this is a common gate stage, the voltage at this node does not swing by more than few mV even at full output. That means the negative supply can simply be tied to ground, and the lower resistor values adjusted accordingly, and tada, half the power dissipation with absolutely no functional change to the circuit itself!
This means we need two less regulators, and we will now be dissipating roughly 23W at 45V rather than the previous 45W! I would imagine this will be a welcome change to anyone currently struggling with heat!
If you currently have the stock NTD1 as shown in the build thread schematic, all you need to do is replace the four 400 ohm resistors with 15 ohm resistors, and short the negative supply to ground by shorting across the pair of 2.2uF decoupling caps on that rail. You also have to make sure you remove the regulators for both negative rails.
This also means you probably only need one transformer and you can use each secondary to power each channel since we now only need one supply.
I have tried this, and measured it, and it works perfectly! I strongly suggest everyone else take the time to do the same. Consider it an act of kindness to the environment
Cheers,
Owen
Hi Guys,
It has been a long time since there were any updates on this page, but I've recently taken this design out and dusted it off to take a fresh look at how I can reduce the power consumption without reducing the performance.
I was running some simulations when I had a bit of a "Aha!" moment.
Can anyone here take any guesses? It's painfully obvious as soon as you see it.
Take a look at the negative supply, and ask yourself, "What is this doing for us?".
The answer is... nothing, except dissipating 50% of the current power dissipation.
The voltage at the source of each fet is roughly 1.75VDC, and since this is a common gate stage, the voltage at this node does not swing by more than few mV even at full output. That means the negative supply can simply be tied to ground, and the lower resistor values adjusted accordingly, and tada, half the power dissipation with absolutely no functional change to the circuit itself!
This means we need two less regulators, and we will now be dissipating roughly 23W at 45V rather than the previous 45W! I would imagine this will be a welcome change to anyone currently struggling with heat!
If you currently have the stock NTD1 as shown in the build thread schematic, all you need to do is replace the four 400 ohm resistors with 15 ohm resistors, and short the negative supply to ground by shorting across the pair of 2.2uF decoupling caps on that rail. You also have to make sure you remove the regulators for both negative rails.
This also means you probably only need one transformer and you can use each secondary to power each channel since we now only need one supply.
I have tried this, and measured it, and it works perfectly! I strongly suggest everyone else take the time to do the same. Consider it an act of kindness to the environment
Cheers,
Owen
Hi Do,
You are correct, the 2.2uF caps are no longer required. They should be removed and replaced with either small copper shorts, or you can use the appropriate size of 0 ohm resistor if you want it to look pretty.
As for re-adjusting, I would certainly suggest it. It will be close to whatever it was before, but it's still prudent to double check and re-adjust everything.
Also, as qusp pointed out some time ago, the best way to set the voltage at the source is to measure the AVCC voltage on your actual BII/BIII/Acko unit, divide it by 2, and set the voltage at the source to match. The BII and BIII both use closer to 3.5V for AVCC which means the voltage at the source (input of the NTD1) should be set to 1.75V.
I will see if I can get a picture of my modified (and now much cooler running!) unit posted tonight.
Regards,
Owen
You are correct, the 2.2uF caps are no longer required. They should be removed and replaced with either small copper shorts, or you can use the appropriate size of 0 ohm resistor if you want it to look pretty.
As for re-adjusting, I would certainly suggest it. It will be close to whatever it was before, but it's still prudent to double check and re-adjust everything.
Also, as qusp pointed out some time ago, the best way to set the voltage at the source is to measure the AVCC voltage on your actual BII/BIII/Acko unit, divide it by 2, and set the voltage at the source to match. The BII and BIII both use closer to 3.5V for AVCC which means the voltage at the source (input of the NTD1) should be set to 1.75V.
I will see if I can get a picture of my modified (and now much cooler running!) unit posted tonight.
Regards,
Owen
Hi Do,
Ooops! I should be clear about this. I'm referring to the 2.2uF decoupling caps on the power supply rail (C36, C37, C42, C43) and not the 22uF output coupling caps!
The output must still be AC coupled using the 22uF film caps.
Essentially what this modification is doing is shorting the negative supply to ground (using the above mentioned caps) and reducing R16, R17, R25, and R26 from 400R to 15R in order to maintain the same bias current in the design (116mA).
As you can see if you look at the schematic, we need to drop roughly 46.75V across the 400 ohm resistor to get a bias current of 116mA while keeping the source of the fet at +1.75V. This results in a power dissipation of 5.4W per resistor. All we're doing here is grounding the negative supply so that we only have to drop 1.75V across the lower resistor, which reduces power dissipation down to 0.2W for the same 116mA bias current. This saves about 21W of dissipation and does not change the circuit operation at all.
Regards,
Owen
Ooops! I should be clear about this. I'm referring to the 2.2uF decoupling caps on the power supply rail (C36, C37, C42, C43) and not the 22uF output coupling caps!
The output must still be AC coupled using the 22uF film caps.
Essentially what this modification is doing is shorting the negative supply to ground (using the above mentioned caps) and reducing R16, R17, R25, and R26 from 400R to 15R in order to maintain the same bias current in the design (116mA).
As you can see if you look at the schematic, we need to drop roughly 46.75V across the 400 ohm resistor to get a bias current of 116mA while keeping the source of the fet at +1.75V. This results in a power dissipation of 5.4W per resistor. All we're doing here is grounding the negative supply so that we only have to drop 1.75V across the lower resistor, which reduces power dissipation down to 0.2W for the same 116mA bias current. This saves about 21W of dissipation and does not change the circuit operation at all.
Regards,
Owen
Hi Owen,
thank you for this information!
Normaly the distortion of this stage will be higher using a 15R instead of 400R.
I thought about changing the power supply and the source resistor more than one year before and was canceling this idea.
Can you please make a simulation with high signal input level (higher current) comparing THD+N
If I find the time for it this weekend, I also will make a new simulation with Multisim.
May DAC runs fine since a long time now. I am very happy with the sound quality. My output copplers are 100µF Black Gate parallel to 56nF silver Mica and a 3,3nF KP capacitor. The red bipolar Black Gate condensors are very important for the SQ. I know 100µF is much, but with big values there is a audible difference in bass SQ. 47µF will also be ok.
The most important update was changing the four Trident shunt regulaters to the newer versions 3.3V to V3 and 1.2V to V3 and the AVCC to V2.1
The AVCC V2.1 needs a long burn in (at least 20 hours) to sound better than the old version.
But then you will get much more transparency. The greatest dfference of the NTD1 compared with other DACs is the incredible "live sound"
Other DACs who use OPVs in the output stages are sounding "compressed" with less dynamic compared to the NTD1.
thank you for this information!
Normaly the distortion of this stage will be higher using a 15R instead of 400R.
I thought about changing the power supply and the source resistor more than one year before and was canceling this idea.
Can you please make a simulation with high signal input level (higher current) comparing THD+N
If I find the time for it this weekend, I also will make a new simulation with Multisim.
May DAC runs fine since a long time now. I am very happy with the sound quality. My output copplers are 100µF Black Gate parallel to 56nF silver Mica and a 3,3nF KP capacitor. The red bipolar Black Gate condensors are very important for the SQ. I know 100µF is much, but with big values there is a audible difference in bass SQ. 47µF will also be ok.
The most important update was changing the four Trident shunt regulaters to the newer versions 3.3V to V3 and 1.2V to V3 and the AVCC to V2.1
The AVCC V2.1 needs a long burn in (at least 20 hours) to sound better than the old version.
But then you will get much more transparency. The greatest dfference of the NTD1 compared with other DACs is the incredible "live sound"
Other DACs who use OPVs in the output stages are sounding "compressed" with less dynamic compared to the NTD1.
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Hi OPC,
It is a really good job. Nice!
From this long long thread, I can't find a AP test in FFT view which the ES9006/9018 series chip provide -30dBFS ~ -60dBFs output level.
Why do I care about this FFT measurement is that Taiwan DIYer find this issue in theire project.
Would you help to have a test? Thank you ^_^
regards
Paul
It is a really good job. Nice!
From this long long thread, I can't find a AP test in FFT view which the ES9006/9018 series chip provide -30dBFS ~ -60dBFs output level.
Why do I care about this FFT measurement is that Taiwan DIYer find this issue in theire project.
Would you help to have a test? Thank you ^_^
regards
Paul
Hi Paul,
I'm going to be testing with this DAC again next week to prove out the isolator/reclocker from Acko, so I can grab an FFT for you then.
I'm not sure what you're looking for though... I have tested the ES9018 at all output levels, and have never noticed any abnormalities.
Are you looking for increased distortion, or some sort of gain non-linearity?
Regards,
Owen
I'm going to be testing with this DAC again next week to prove out the isolator/reclocker from Acko, so I can grab an FFT for you then.
I'm not sure what you're looking for though... I have tested the ES9018 at all output levels, and have never noticed any abnormalities.
Are you looking for increased distortion, or some sort of gain non-linearity?
Regards,
Owen
Hi Owen,
The ES9018 has an issue when it is use with OP IV stage. Some level range ~ -30 to -60 dBFS output Will have higher noise floor than original. For example, -30dBFS 1kHz output noise floor is -140dBFS, but when you change the output amplitude to -31dB, the noise floor increase to -130dBFS, together with some harmonics increase.
Notice that the total THD+N is still very low, so that you may not found this issue in common THD+N vs Vout test even you set the test range from -100 to 0dBFS. I suggest you choose some test amplitude randomly, around -30 to -60dBFS range.
I think this issue may comes from poor sink/source current for a common OP based I/V conversion stage. NTD1 have strong source and sink current ability for ES9018 current out pin, so I think this issue may not happen to your system. But I wish youn can check this in NTD1 based ES9018 system, and share the result with us.
Thank youn in advance.
Have a nice day!
Regards
Paul
I made a simulation of the half circuit (unsymmetrical circuit, source was a sinus current 1KHz 0,01A) with Multisim 10 and got a more than twenty times higher value than with 200R /400R and a symmetrical power supply regardless of the level used.
The circuit with only a + 45V power supply and 200R / 15R has a much increased THD+N (distortion), from 0,006% (200R/400R) to 0,13% (200R/15R)
I am not wondering about this result, because the 400R source resistor is responsible for the negative feedback of the circuit.
Higher value, more negative feedback, lower distortion.
The circuit with only a + 45V power supply and 200R / 15R has a much increased THD+N (distortion), from 0,006% (200R/400R) to 0,13% (200R/15R)
I am not wondering about this result, because the 400R source resistor is responsible for the negative feedback of the circuit.
Higher value, more negative feedback, lower distortion.
Hi Salomon,
You are indeed correct, and my simulations from LTSpice seem to agree that the distortion does indeed increase due to the reduced emitter degeneration caused by the lower resistor value.
My simulations are nowhere near as bad as what you got, but still show a significant detrimental effect. The circuit with the bipolar supply shows a 3rd harmonic at -122dB, while the circuit with the single supply and lower resistance shows a 3rd harmonic of -96dB. Both sims have no even order harmonics due to the differential nature of the circuit.
My initial simulation was done with a "simplified" model that didn't catch the above effects.
On the bright side, however, the "simplified" simulation has tipped me off to a few things that can be done to bring the performance of the single supply circuit back in line with the bipolar one. It would appear the same tricks can also be used to further improve the performance of the bipolar supply circuit.
I've run all the simulations, but I really need to test everything carefully in an actual circuit to make sure it jives with reality.
In the meantime, however, I would like to suggest not eliminating the negative supply or changing the resistor just yet, until I confirm with measurements. If you do so in the circuit as is, you will suffer a performance hit.
Measurements to follow this week!
Cheers,
Owen
You are indeed correct, and my simulations from LTSpice seem to agree that the distortion does indeed increase due to the reduced emitter degeneration caused by the lower resistor value.
My simulations are nowhere near as bad as what you got, but still show a significant detrimental effect. The circuit with the bipolar supply shows a 3rd harmonic at -122dB, while the circuit with the single supply and lower resistance shows a 3rd harmonic of -96dB. Both sims have no even order harmonics due to the differential nature of the circuit.
My initial simulation was done with a "simplified" model that didn't catch the above effects.
On the bright side, however, the "simplified" simulation has tipped me off to a few things that can be done to bring the performance of the single supply circuit back in line with the bipolar one. It would appear the same tricks can also be used to further improve the performance of the bipolar supply circuit.
I've run all the simulations, but I really need to test everything carefully in an actual circuit to make sure it jives with reality.
In the meantime, however, I would like to suggest not eliminating the negative supply or changing the resistor just yet, until I confirm with measurements. If you do so in the circuit as is, you will suffer a performance hit.
Measurements to follow this week!
Cheers,
Owen
Hi Owen,
Thanks for your great job and your great support!
We are waiting for the measurement ^_^
BTW, is this circuit will get better performance if I found some other MOSFET which has higher transconductor? Or lower Idd, but higher transconductor and higher source resistor can be applied which provide deeper local negative feedback as 400R do now.
Thank you!
Regards
Paul
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