2stageEF high performance class AB power amp / 200W8R / 400W4R

[AndrewT]

.......................
I had earlier been surprised at how much the loop gain. was affected when I added an "RF filter" to the input.
At least, I intended an RF filter, the improved stability was a bonus.
I didn't think of it as "in the loop", do you have a simple qualitative explanation for this?...........

Is it simply very low Source Impedance as a load for the input stage?

 

[31697B]

Remember that in conduction, a BJT's B-E capacitance increases greatly, and is in addition to the 90 degrees LTP output current which appears as a capacitive Ib of the LTP. A BC550C LTP can have a real and/or virtual 400pF or so across the bases while conducting. The datasheet Cib curves are for a REVERSE-biased B-E junction - it actually increases with Vbe.

At RF, the base current through this capacitance is significant. So say your effective differential capacitance through the LTP bases is 400pF. You use a 390pF input decoupler or LP filter. Well, if you have no source connected and the input isn't shorted, then the input differential capacitance forms a capacitive voltage divider and your LTP transconductance at RF is halved!

Hopefully that makes sense, or provides enough information you can replicate it in simulation.

The source impedance at RF is very much "in the loop", and the same applies for the feedback side of the LTP. It gets much more important when you push the ULGF high.

Just a follow-on comment.... when terminating a source for best square-wave corner fidelity (nice square corner without mis-match affects - over-shoot etc) the term Z is pretty much the rbb plus Re. Thus, in 50 Ohms systems the transistors input C makes the leading edge (high freqs) go straight thru to the Re as the source load Z.

THx-RNMarsh

 

[kgrlee]

Toni and I swapped a few emails on exactly this subject just a few days back.
I had earlier been surprised at how much the loop gain. was affected when I added an "RF filter" to the input.
At least, I intended an RF filter, the improved stability was a bonus.
I didn't think of it as "in the loop", do you have a simple qualitative explanation for this?

I find kean's explanation a bit difficult to understand but I'm sure it makes sense.

I prefer to think of it this way. One major path through the LTP is actually an Emitter Follower driving a Common Base stage. The grounding (or lack of grounding) of the CB stage changes the gain through the LTP.

(The other i/p of the LTP can be considered similarly with superposition.)

The difference in LF Loop Gain, with input shorted or not, may be more than 10dB.

For the HF case, many commercial amps are unstable with OC i/ps if you remove the 'RF filter'.

Encountering this 3 decades ago was one of the reasons I wrote my own 'linear' circuit analysis package.
_____________________

I apologise for being quiet but the level of this thread is now such that serious work is required to make any worthwhile contribution.

I'm actually in the process of moving away from the 'Blameless' topology (of which IMHO, Toni's is the best implementation) towards an 'older' favourite .. mainly for overload & recovery reasons.

But I haven't had a chance to do any serious work on it. Beach bums have a hard life

Toni sets a very high bar for any 'improvements'.

 

[keantoken]

To give a sense of scale, an LTP has a differential resistance, modeled as a resistor between the bases, which is equal to the total Re of the LTP multiplied by the Hfe of the transistors used. For a BC5xxC LTP at 3mA per transistor, this is roughly 10.4k.

If you then have a source resistance of 10.4k, the same current that flows through the differential resistance will flow through that, producing a voltage equal to the LTP differential voltage across it. So at the NFB side of the LTP we now have twice the error voltage - the LTP error voltage, and in addition to it the error voltage "mirrored" across the 10.4k source impedance.

The same applies at HF if you replace the resistors with capacitors, and is why input decoupling is good practice for feedback circuits. Having some real numbers/equations here however allows us to know exactly how much decoupling we need and how much is too much.

Higher gain BJTs and Jfets suffer less from this problem at LF. A 2N5551 LTP for instance will have a differential resistance of about 2.2k, so will be more sensitive. However a transistor with high Cbe may need more input decoupling even if it has greater gain.

I hope this explains it better.

 

[Dave Zan]

...I hope this explains it better.

Richard's explanation is more the way I think about it.
But no one so far has caused a
Just to be specific.
Here are the inner and outer loop gains for my complementary IPS amplifier (still private, sorry).
Red and white are before a 6nF capacitor is added to the LTP input.
Yellow and Green are after, obviously.
Improvement in phase, not sure if that is entirely explained by the small increase in gain way up in frequency.

Best wishes
David

 

[keantoken]

Adding to my last post, if at the frequency in question the differential LTP impedance is capacitive, and the source impedance is resistive, then your effective LTP transconductance will be inductive. If the situation is reversed, the LTP transconductance will be capacitive. These change the phase of the loop gain.

Note that the source impedance includes everything at the input node, not just the input resistor. So for instance if the transistor's Cbc is 22pF and the input resistor is 33k, at RF (above the corner frequency) it will be capacitive, and since the LTP differential impedance at RF is capacitive as well, there will be a reduction in transconductance but no change in phase.

How your feedback loop responds to the source impedance depends on the phase of the currents through the LTP, as these will be reflected in the differential impedance through Hfe.

 

[astx]

...
Here are the inner and outer loop gains for my complementary IPS amplifier (still private, sorry).
...

Awesome, more as 80db gain at 20kHz. Mine has about 60db.
What is your amplifiers gain?

 

[Dave Zan]

Awesome, more as 80db gain at 20kHz. Mine has about 60db.
What is your amplifiers gain?

Thank you. The trade-off is a ULGF of 5 MHz on the outer loop.
I believe this is feasible with the PCB layout I have.
Modern motherboards do 1000 MHz so I have learned a few tricks, the build will tell.

The gain for the development model is about 50 = 34 dB
This is to allow for the 600 W bass amp to be driven to full power by 1 V, approximately.
But the loop gain plot is actually from the 100 W amp, I need to fine tune this stuff.

Best wishes
David

 

[dadod]

Thank you. The trade-off is a ULGF of 5 MHz on the outer loop.
I believe this is feasible with the PCB layout I have.
Modern motherboards do 1000 MHz so I have learned a few tricks, the build will tell.

The gain for the development model is about 50 = 34 dB
This is to allow for the 600 W bass amp to be driven to full power by 1 V, approximately.
But the loop gain plot is actually from the 100 W amp, I need to fine tune this stuff.

Best wishes
David

Hi David,
When you are going to show your schematic, I'm very interested, specially what tricks you use in the layout? ULGF of 5 MHz, is that with mosfet OPS or BJT?
Best regards
Damir

 

[Dave Zan]

...show your schematic, I'm very interested, specially what tricks you use in the layout? ULGF of 5 MHz, is that with mosfet OPS or BJT?

Not sure whether to show the schematic in Linear Audio or here first, has a neat CMCL that a friend invented, so want to respect his choice too.
Layout is all about minimisation of inductance (= minimised loop area.)
PC motherboards can be routinely made to work at 1000 MHz so they really understand this. 5 MHz should be easy
The OPS is BJT - OnSemi NJL4302/4281 ThermalTrak.

Best wishes
David

 

[kgrlee]

... has a neat CMCL that a friend invented, so want to respect his choice too.

Duu.uuh!

Was is das, Dave? Mee ble wid all dis TLAs

Are you using more than 2 layers (top & bottom) for your PCB?

 

[keantoken]

I think he means Common Mode Control Loop.

 

[astx]

...
5 MHz should be easy
The OPS is BJT - OnSemi NJL4302/4281 ThermalTrak.
...

CFA topology?

 

[kgrlee]

I think he means Common Mode Control Loop.

Got a link for this?

 

[keantoken]

I thought Bonsai published a schematic with a CMCL in the VAS to keep it biased right, to get around the Randy Slone "undefined VAS current" problem with fully symmetrical dual LTP+CM+beta-enhanced-VAS circuits. Maybe it was Edmond Stuart or someone else, I can't find it on Bonsai's site.

Of course CMCL doesn't mean any specific stage, if you wanted you could pepper CMCL's all throughout an amplifier. But my best guess is that mostly they are used for stabilizing VAS current when it is not already well-defined by the topology.

 

[kgrlee]

I thought Bonsai published a schematic with a CMCL in the VAS to keep it biased right, to get around the Randy Slone "undefined VAS current" problem with fully symmetrical dual LTP+CM+beta-enhanced-VAS circuits. Maybe it was Edmond Stuart or someone else, I can't find it on Bonsai's site.

If it's to stabilise enhanced symmetrical VAS current, Bob Cordell's old MOSFET AES amp was the first application of this I've seen.

I'm playing with it now to get away from Blameless. Nice overload & recovery properties. Can't get time to do serious work on it.

 

[Bonsai]

I thought Bonsai published a schematic with a CMCL in the VAS to keep it biased right, to get around the Randy Slone "undefined VAS current" problem with fully symmetrical dual LTP+CM+beta-enhanced-VAS circuits. Maybe it was Edmond Stuart or someone else, I can't find it on Bonsai's site.

Of course CMCL doesn't mean any specific stage, if you wanted you could pepper CMCL's all throughout an amplifier. But my best guess is that mostly they are used for stabilizing VAS current when it is not already well-defined by the topology.

Not me Richard. I did the CFA enhanced beta TIS, EF3 with AFEC with TMC comp for 600 ppb at 20 kHz at 400W. It's somewhere on the CFA thread.

I am tending nowadays towards simple, elegant CFA with inherent full power distortion of 70-80 ppm and low order harmonic. If I think it needs single digit ppm, I'll add AFEC. All my listening tests on my 5 amplifiers tell it's not.

Such are the vagaries of amplifier design . . .

 

[Bonsai]

BTW if anyone is interested, I've extensively updated my write up on AFEC, adding the system loop gain plots.

Turns out that AFEC loop gain, when optimized, resembles somewhat TPC. Link below

Distortion Reduction in Audio Amplifiers: AFEC

 

[Bonsai]

simulation numbers

Harmonic Frequency Fourier Normalized Phase Normalized
Number [Hz] Component Component [degree] Phase [deg]
1 2.000e+04 8.358e+01 1.000e+00 -1.60° 0.00°
2 4.000e+04 1.057e-04 1.264e-06 -22.36° -20.76°
3 6.000e+04 6.984e-05 8.356e-07 138.42° 140.02°
4 8.000e+04 5.223e-06 6.249e-08 -166.31° -164.71°
5 1.000e+05 3.296e-05 3.944e-07 31.18° 32.77°
6 1.200e+05 1.531e-05 1.831e-07 -153.94° -152.34°
7 1.400e+05 5.030e-05 6.018e-07 131.18° 132.78°
8 1.600e+05 2.195e-05 2.626e-07 -144.62° -143.02°
9 1.800e+05 3.848e-05 4.604e-07 113.20° 114.80°
Total Harmonic Distortion: 0.000177%


.step rafec=1e+012
N-Period=1
Fourier components of V(vout)
DC component:-0.512084

Harmonic Frequency Fourier Normalized Phase Normalized
Number [Hz] Component Component [degree] Phase [deg]
1 2.000e+04 8.352e+01 1.000e+00 -1.57° 0.00°
2 4.000e+04 8.605e-05 1.030e-06 0.64° 2.21°
3 6.000e+04 6.167e-04 7.384e-06 68.43° 70.00°
4 8.000e+04 4.552e-05 5.451e-07 136.73° 138.30°
5 1.000e+05 1.868e-04 2.237e-06 -43.25° -41.68°
6 1.200e+05 6.435e-05 7.705e-07 122.81° 124.38°
7 1.400e+05 2.162e-04 2.588e-06 54.93° 56.51°
8 1.600e+05 8.265e-05 9.896e-07 144.93° 146.51°
9 1.800e+05 1.385e-04 1.658e-06 41.44° 43.01°
Total Harmonic Distortion: 0.000848%


1st THD # is with AFEC at 440W RMS into 8 Ohms at 20 kHz

2nd THD # is with AFEC switched out - same drive and load conditions.


#'s below are for 3 Ohm load with AFEC

Harmonic Frequency Fourier Normalized Phase Normalized
Number [Hz] Component Component [degree] Phase [deg]
1 2.000e+04 8.358e+01 1.000e+00 -1.60° 0.00°
2 4.000e+04 1.030e-04 1.233e-06 -22.46° -20.86°
3 6.000e+04 7.212e-05 8.629e-07 131.00° 132.60°
4 8.000e+04 7.690e-06 9.200e-08 165.83° 167.43°
5 1.000e+05 6.498e-05 7.775e-07 29.77° 31.37°
6 1.200e+05 1.502e-05 1.797e-07 155.55° 157.15°
7 1.400e+05 6.988e-05 8.361e-07 82.63° 84.23°
8 1.600e+05 2.143e-05 2.564e-07 152.24° 153.84°
9 1.800e+05 1.074e-04 1.284e-06 60.25° 61.85°
Total Harmonic Distortion: 0.000231%


#'s below are for non-AFEC

.step rafec=1e+012
N-Period=1
Fourier components of V(vout)
DC component:-0.512149

Harmonic Frequency Fourier Normalized Phase Normalized
Number [Hz] Component Component [degree] Phase [deg]
1 2.000e+04 8.352e+01 1.000e+00 -1.57° 0.00°
2 4.000e+04 9.718e-05 1.164e-06 22.24° 23.81°
3 6.000e+04 6.256e-04 7.491e-06 60.10° 61.67°
4 8.000e+04 5.472e-05 6.552e-07 112.64° 114.21°
5 1.000e+05 3.753e-04 4.493e-06 -45.88° -44.31°
6 1.200e+05 6.942e-05 8.312e-07 68.89° 70.46°
7 1.400e+05 3.048e-04 3.650e-06 6.24° 7.81°
8 1.600e+05 6.467e-05 7.743e-07 85.55° 87.12°
9 1.800e+05 3.739e-04 4.477e-06 -12.22° -10.65°
Total Harmonic Distortion: 0.001062%


The distortion at 225 W 20 kHz 8 Ohms is 1.27ppm with AFEC

 

[Dave Zan]

CFA...?

Not really. The foundation of a "CFA" is the lower impedance on the feedback node. So I use a classic VFA circuit but pull the impedance of that node down with a low resistance in the feedback divider.
Best of both worlds.

... a link for this?

The abbreviation was popularised here by Edmond Stuart.
A search of this forum for "CMCL" will turn up a lot of useful stuff.

...more than 2 layers (top & bottom) for your PCB?

To avoid a hijack of Toni's thread I think it is better to discuss this here http://www.diyaudio.com/forums/solid-state/261973-middlebrook-gft-probe-3.html#post4076143

where I have already posted loop gain plots for the CMCL and discussed the board layout a little.

Best wishes
David