24 bit ADC interfacing with ARM using I2S

[sukhdeep]

hi,
i want to interface 24 bit ADC interfacing with ARM using I2S protocol. i am using ADC CS5361.if i shall enable 32 bit word width. then how can it read 24 bit data.because it will change WS after recieving 32 bit data.but ADC will give 24 bit after that it expected that WS should be changed to show 24 bit data of another channel.
how can i manage this problem?
Kindly help me.
i will be grateful for your help.
Thanks

 

[FastEddy]

I'm sure you have already seen the "evaluation board" data sheet: http://www.cirrus.com/en/pubs/rdDatasheet/cs5361eb-4.pdf

" ... .because it will change WS after receiving 32 bit data ..."

You may have to address this to Cirrus Logic ... I may have missed something ... the output is digital 24 bit and the device "receives" analog ... Maybe I should read more ...

I just received an "evaluation kit" from TI ( 24 bit ADC from single or multi channel input = http://focus.ti.com/docs/toolsw/folders/print/ads1271evm-pdk.html ) and of course there are several ways to program it for the optional outputs, etc. ...

 

[sukhdeep]

problem in i2s

first of all thanks for reply.

I am using CS5361 for picking data from left and right channel using I2S protocol of LPC2378. but for testing purpose, i have made left channel ground and applying analog signal on right channel to check conflict in data picking. i have found that when i am picking data. ocassionally i shows data oon left channel. while i am not giving any data on left channel. I am operating CS5361 with following settings
MCLK=12Mhz
LRCLK=46.875khz.
in single speed mode.
why it shows, why this shows this kind of error. if i am operating CS5361 in double speed mode. then data conflict between right and left channel increases.

how can i avoid this problem.
Regards
Sukhdeep Singh.