Ian,
in my opinion the FPGA should do the "dirty" job only, so I believe that the clock division should be kept far from it, even with a pair of synchronous counters.
This is what we have done in our FIFO Lite isolating the return to the FPGA via optocouplers (even the master clock is optically isolated).
Maybe I'm wrong but will see the measurement result soon.
The regenerative divider remains the only option to get the best result, we expect better close in phase noise performance of the divided clock against the master clock, since theoretically the division improves the phase noise.
IMHO the FPGA should be slaved to the crucial clock for the DAC, so the BCK or the LRCK depending on the DAC, because the crucial signal should feed directly the DAC (master clock divided by n) without crossing the FPGA.
We have choosen the LRCK because our new discrete DACs switch on the LRCK.
DACs operating on the master clock don't need a FIFO, just keep the master clock as clean as possible, so using a USB to I2S converter based on a low noise oscillator should be enough.
Digital electronics in the end always comes back to analog issues.
in my opinion the FPGA should do the "dirty" job only, so I believe that the clock division should be kept far from it, even with a pair of synchronous counters.
This is what we have done in our FIFO Lite isolating the return to the FPGA via optocouplers (even the master clock is optically isolated).
Maybe I'm wrong but will see the measurement result soon.
The regenerative divider remains the only option to get the best result, we expect better close in phase noise performance of the divided clock against the master clock, since theoretically the division improves the phase noise.
IMHO the FPGA should be slaved to the crucial clock for the DAC, so the BCK or the LRCK depending on the DAC, because the crucial signal should feed directly the DAC (master clock divided by n) without crossing the FPGA.
We have choosen the LRCK because our new discrete DACs switch on the LRCK.
DACs operating on the master clock don't need a FIFO, just keep the master clock as clean as possible, so using a USB to I2S converter based on a low noise oscillator should be enough.
Digital electronics in the end always comes back to analog issues.
You can see it on the board written under the word ultimate.
I have the first edition, on the Audiophonics site the Q2 version is shown on the Q3 order field.
See pictures.
@Ian, on the Audiophonics website they announce the Q3 version will be available on 16 sept. Is this correct?
I have the first edition, on the Audiophonics site the Q2 version is shown on the Q3 order field.
See pictures.
@Ian, on the Audiophonics website they announce the Q3 version will be available on 16 sept. Is this correct?
Attachments
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It's on the board. See picture.
Just recently bought, didn't knew a new version was almost there.
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@Supersurfer
FifoPi Q3 are under production. Hopefully they will be available in next week.
Regards,
Ian
StationPi PCB
StationPi PCB
1. Two stacks configuration. Before FifoPi is the digital stack. After FifoPi is the audio stack.
2. Double ground shielding walls, four shield layers in total
3. Power GPIO directly
4. Great to build DAC or digital transport
StationPi_PCB by Ian, on Flickr
StationPi_FifoPi_TransportPi by Ian, on Flickr
Ian
StationPi PCB
1. Two stacks configuration. Before FifoPi is the digital stack. After FifoPi is the audio stack.
2. Double ground shielding walls, four shield layers in total
3. Power GPIO directly
4. Great to build DAC or digital transport
StationPi_PCB by Ian, on Flickr
StationPi_FifoPi_TransportPi by Ian, on Flickr
Ian
What the height of the heat sink? I can also open a window if it is too high.
Any other thought?
Regards,
Ian