Soekris' DAC implementations

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You're completely wrong that you can use fixed clocks, and the latch clock is the most important clock.... Sorry, you seems to know oscillators, but not much about digital audio....

The design of the dam1021 is based on a variable oscillator, you need that when using a small FIFO and the digital PLL to track incoming sample rates. If you think people are complaining a little now, then figure what would happen if I used your way of controlling the clock, talk about jitter by dropping clock pulses....

The dam1021 has been designed to be flexible and easy to use, so no long FIFO, don't work with video or live settings, it can tolerate crappy clocks, like SPDIF sources or the RPi.

I believe you are completely wrong, you are justifyiing the cheap solution you have chosen (simply business) with some statements that are not true.

There is no reason to use a small FIFO if you are really looking for jitter elimination, simply you have saved Eur 10 to implement a suitable SRAM. Please, ask yourself why Ian use SRAM and a larger FIFO. I know, the lower the cost the greater the profit.
PLL adds jitter rather than eliminates it.

As I already stated there is no issue using a pair of fixed oscillator, one for each sample rate family. You don't need any PLL in your design using a 4-8Mb SRAM, as Ian does.
I repeat, the FPGA does easily the job starting from a fixed frequency, or a pair if you consider the different sample rate family. But obviously a single Si514 is far more cheaper than a pair of good oscillators. Again a business choice, not technically supported.

There is no reason to track incoming sample rates, a larger FIFO solve the issue, then the FPGA does the rest of the job providing data to the DAC at the suitable bit clock frequency, simply keeping the master clock frequency greater or equal to the maximum bit clock frequency. 28 bit x 384kHz max sample rate = 10.752 MHz, so a pair of good oscillators at 11.2896 and 12.288 MHz are enough, maybe a pair of 5/6 MHz multiplied by 2 to get the better phase noise performance as possible. But again, they are more expensive than the cheaper Si514.

And yes, the latch clock is the most important signal in your design. Although you have not shared the schematic, since your is a commercial project, I can reasonably assume this statement because you are using the 595s as the bit switches of the R2R DAC. But if you don't agree please elaborate a little the reasons.

Finally, if you claim that your projectual choice using the Si514 was done to keep the cost as lower as possible I totally agree, but please avoid to to attribute the choice to technical reasons.
 
I believe you are completely wrong, you are justifyiing the cheap solution you have chosen (simply business) with some statements that are not true.

There is no reason to use a small FIFO if you are really looking for jitter elimination, simply you have saved Eur 10 to implement a suitable SRAM. Please, ask yourself why Ian use SRAM and a larger FIFO. I know, the lower the cost the greater the profit.
PLL adds jitter rather than eliminates it.

As I already stated there is no issue using a pair of fixed oscillator, one for each sample rate family. You don't need any PLL in your design using a 4-8Mb SRAM, as Ian does.
I repeat, the FPGA does easily the job starting from a fixed frequency, or a pair if you consider the different sample rate family. But obviously a single Si514 is far more cheaper than a pair of good oscillators. Again a business choice, not technically supported.

There is no reason to track incoming sample rates, a larger FIFO solve the issue, then the FPGA does the rest of the job providing data to the DAC at the suitable bit clock frequency, simply keeping the master clock frequency greater or equal to the maximum bit clock frequency. 28 bit x 384kHz max sample rate = 10.752 MHz, so a pair of good oscillators at 11.2896 and 12.288 MHz are enough, maybe a pair of 5/6 MHz multiplied by 2 to get the better phase noise performance as possible. But again, they are more expensive than the cheaper Si514.

And yes, the latch clock is the most important signal in your design. Although you have not shared the schematic, since your is a commercial project, I can reasonably assume this statement because you are using the 595s as the bit switches of the R2R DAC. But if you don't agree please elaborate a little the reasons.

Finally, if you claim that your projectual choice using the Si514 was done to keep the cost as lower as possible I totally agree, but please avoid to to attribute the choice to technical reasons.

Cost isn't the only issue, have a set of the fine Epson SG-210 fixed oscillators her, they're used in the dac1101, they're $0.43 each, but I NEED the programmable clock to support SPDIF....

I can see you totally ignore the reason for a short FIFO, if I wanted a larger FIFO, I just use more of the FPGA's RAM Blocks.... Anyway, most of my newer designs use the higher performance si570, you have problem with that part too ? MSB Technology and Rockna don't....
 
Cost isn't the only issue, have a set of the fine Epson SG-210 fixed oscillators her, they're used in the dac1101, they're $0.43 each, but I NEED the programmable clock to support SPDIF....

I can see you totally ignore the reason for a short FIFO, if I wanted a larger FIFO, I just use more of the FPGA's RAM Blocks.... Anyway, most of my newer designs use the higher performance si570, you have problem with that part too ? MSB Technology and Rockna don't....

I wonder how you can claim that the Epson SG-210 is a fine oscillator, the datasheet does not show any phase noise plot, and the only declared data is -145dBc at 1kHz from the carrier. I believe you have not clear what means "fine oscillator", please take a look at the plot I published about a Driscoll oscillator, this is a fine oscillator, not the Epson neither the Si570 that exhibits -125 dBc at 100 Hz from the carrier, while the Driscoll reaches -125 dBc at 10 Hz from the carrier.

And please avoid to compare RMS jitter if the integration bandwidth used in the measurements is different, as you can surely know the RMS phase jitter increases a bit when measuring close to the carrier.

Again, I understand your projectual choices from the business point of view, but you cannot claim that these choises was driven by technical reasons. A fine oscillator like the Driscoll one probably costs more than Eur 100, so a pair is at least Eur 200, while the Si514 and Si570 are 10-15 Eur parts.
 
About SPDIF, like Ian has done you can provide an SPDIF to I2S converter, external or internal. So no need of programmable clock to support SPDIF.

Since I share my designs, an interface like the one in the attached document can easily drive your R2R DAC. Only a pair of fixed oscillators, no need of programmable clock.
This is the way to keep the RMS jitter as lower as possible, supported by several technical reasons. But obviously it costs much more than the solution you have implemented, so no business reasons from your commercial point of view, while there are many reasons from the diyer's point of view.
 

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About SPDIF, like Ian has done you can provide an SPDIF to I2S converter, external or internal. So no need of programmable clock to support SPDIF.

Since I share my designs, an interface like the one in the attached document can easily drive your R2R DAC. Only a pair of fixed oscillators, no need of programmable clock.
This is the way to keep the RMS jitter as lower as possible, supported by several technical reasons. But obviously it costs much more than the solution you have implemented, so no business reasons from your commercial point of view, while there are many reasons from the diyer's point of view.

I regularly watch Music Videos on youtube, so I can't use a DAC with a long delay.... So when I designed the dam1021, I wanted short delay, ruling out that crappy idea of long FIFO's, and I wanted SPDIF support so I can use my CD player.... You're welcome to design a DAC using YOUR ideas, just don't try to push YOUR ideas on my DACs....

And yes, I sell my products, at reasonable prices, I keep production cost down, not to make more profits, but so I can sell them at lower cost. I have now sold the dam1021-05 for over five years, and it's still the cheapest discrete R-2R Sign Magnitude DAC module you can buy....
 
I wonder how you can claim that the Epson SG-210 is a fine oscillator, the datasheet does not show any phase noise plot, and the only declared data is -145dBc at 1kHz from the carrier. I believe you have not clear what means "fine oscillator", please take a look at the plot I published about a Driscoll oscillator, this is a fine oscillator, not the Epson neither the Si570 that exhibits -125 dBc at 100 Hz from the carrier, while the Driscoll reaches -125 dBc at 10 Hz from the carrier.

And please avoid to compare RMS jitter if the integration bandwidth used in the measurements is different, as you can surely know the RMS phase jitter increases a bit when measuring close to the carrier.

Again, I understand your projectual choices from the business point of view, but you cannot claim that these choises was driven by technical reasons. A fine oscillator like the Driscoll one probably costs more than Eur 100, so a pair is at least Eur 200, while the Si514 and Si570 are 10-15 Eur parts.

I'm not trying to get as low jitter, or phase noise, as possible. I just want it good enough so it's not what's limit my DACs performance, that what differences a good design, not over designing using fancy expensive parts.... And as I said, the performance of the si570 is good enough for top end DACs, so I'm happy with it too.... You're like those people wanting THD of 0.0001% in their DACs when their speakers have a THD of 0.1%....
In the end it comes down to: how does it sound.
 
Andrea, you seem to be consistently skirting around the issue. If you need low propagation delay, for instance if you need to sync audio and video, that puts a limit on how long a FIFO you can use. What sort of delay does your solution have?

The propagation delay is around 0.5 seconds. There is a price to pay to really eliminate the jitter, surely not using a PLL to track the input frequency that adds jitter itself instead of eliminate it.
You have to decide, longer delay without jitter or shorter delay with jitter. Maybe you have to decide if watching movie or listening to music.

Do you think Ian has included a SRAM with longer delay to spend more money? No, that's the only way to really decrease the jitter.

There is another option but more expensive: you should sync the source to the master clock of the DAC, obviously without any PLL!!
 
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Well, i am no electronic engineer, but i will still give my point of view.

Personally i use my dac for everything, it's just connected to my computer and i use my system for music but also to watch video, movie etc...
So i suppot Soren when he said long Fifo is a pain. You still can change the audio delay in your favorite video player, but what about internet video, and what about people without knowledge that want to use their dac as a standard external sound card...

Also in my case i got problem with the USB interface of my dam1941. Their is something wrong with both my computer and the dam.
The windows driver that soren provide is buggy on windows and often the sound just stop, i have to close the app and disconnect / reconnect the dac to make it work. With standard windows usb audio driver, everything works fine.
In linux, that i use every time except gaming, i have more problem. I got pop when i am playing an audio flux and "doing things" in my computer. For example if i am listening to a song, and when i load an internet page, when the internet page finish to load i often get the "pop", same with other app like file manager etc...
Also the dac sometimes disconnect when a flux stop. If i watch a movie and press the pause button, often my interface (kde) say the dac just disconnect, and i have physically deco / reco the usb cable.
Last thing, if my dam is connected to my computer (linux) and not power on, if i power it on it is often not recognize (i say 2 time over 3). I need to disconnect and reconnect the usb...
Now i am sure the "pop" sound is related to a problem with my motherboard or it's linux driver, because i it not happening with another computer i try. However the recognition problem on linux is common with all my computer (also happening with my dac1101), so it's probably related to the dam usb xmos implantation.

Anyway, all that to say that i was looking for something different to listen to my music, because these "pop" are driving me crazy.

So if you want to build a SBC to act as source for the dam and use the i2s in of the 1941. Most sbc most have a crappy clock like the RPi. It is pointless to use an isolator + fifo with the dam, as the fifo is already handle by the dam it's just lost money. But as the i2s input of the dam1941 is not isolated, you simply need an isolator, and a direct i2s connection or some lvds i2s interface.

The only real alternative would be the beaglebone black with the cronus / hermes, as it the only one to offer a "synchronous flip-flop re-clocking".
But the dam is by nature an asynchronous dac that suppose the source is crappy... So it's impossible to use an external clock with this programmable oscillator thing.
So again the BBB here is just possible but pointless... i am waiting the option to try this BBB with a Soekris dac for years, and i think some people here also.

So maybe... the best would be to cut the apple in half. What about using the programmable clock for the usb and spdif, and have an additionnal i2s in with mclk input...

As you said Soren, you sell product mostly for diy or oem. People like to experiment or at least doing thing differently to differentiate them-self from others...

Also with this option you keep the cost of the dam low, if people want to use their expensive crystal or whatever this is their choice... Also you keep the short fifo for the common interface so the crowd would be happy and people that want something specific for music listening will have their thing...

I don't know if it's possible in a technical perspective, but if it is it would be the solution for everyone to be happy...
 
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The propagation delay is around 0.5 seconds. There is a price to pay to really eliminate the jitter, surely not using a PLL to track the input frequency that adds jitter itself instead of eliminate it.
You have to decide, longer delay without jitter or shorter delay with jitter. Maybe you have to decide if watching movie or listening to music.

Do you think Ian has included a SRAM with longer delay to spend more money? No, that's the only way to really decrease the jitter.

There is another option but more expensive: you should sync the source to the master clock of the DAC, obviously without any PLL!!

Why pay a price ? Just design a good clocking circuit using a good adaptive digital PLL....
Ian designed his circuit without having a short delay as a design goal, which I do.

Remember, DAC's used to use a standard SPDIF receiver, the best of those have 50 pS of jitter.... Some of those DACs were pretty good....

Anyway, low clock jitter is just one parameter in a good flexible discrete R-2R DAC, other parameters are the precision of the resistors, the size of the FPGA (filters), and the power supplies. I balance the parameters for best cost/performance, you just focus on one parameter, low jitter.
 
soekris,

Even in small Qtys its no problem to design a low PN dual frequency Pull-able Clock (with I2C DAC for Frequency control) for around US$5 to US$10 - certainly one that's a magnitude better performance then the SI part... In fact it might even be cheaper then the SI part - or very little difference...

As I mentioned earlier I'd be happy to help...
 
The propagation delay is around 0.5 seconds.

OK, so that's totally useless if you need audio/video sync for any purpose.

There is a price to pay to really eliminate the jitter, surely not using a PLL to track the input frequency that adds jitter itself instead of eliminate it.

It's not black and white as you suggest. Sure PLLs reduce jitter rather than totally eliminate it, but a well designed PLL can do a very good job.
 
soekris,

Even in small Qtys its no problem to design a low PN dual frequency Pull-able Clock (with I2C DAC for Frequency control) for around US$5 to US$10 - certainly one that's a magnitude better performance then the SI part... In fact it might even be cheaper then the SI part - or very little difference...

Which Si part is that? The 570 is around -125dBc at 100Hz, can that be bettered cheaply?
 
soekris,

Even in small Qtys its no problem to design a low PN dual frequency Pull-able Clock (with I2C DAC for Frequency control) for around US$5 to US$10 - certainly one that's a magnitude better performance then the SI part... In fact it might even be cheaper then the SI part - or very little difference...

As I mentioned earlier I'd be happy to help...

The si514 is pullable 1000 ppm, and that what I would need.... I don't believe you can pull a xtal that much....
 
Why pay a price ? Just design a good clocking circuit using a good adaptive digital PLL....
Ian designed his circuit without having a short delay as a design goal, which I do.

Remember, DAC's used to use a standard SPDIF receiver, the best of those have 50 pS of jitter.... Some of those DACs were pretty good....

Anyway, low clock jitter is just one parameter in a good flexible discrete R-2R DAC, other parameters are the precision of the resistors, the size of the FPGA (filters), and the power supplies. I balance the parameters for best cost/performance, you just focus on one parameter, low jitter.

The jitter of the SPDIF is not an issue since the reclocker decreases it as lower as possible, obviously if you use a low jitter clock, not the Si parts.
About the precision of the resistors I have already said in your main thread, you are reaching not more than 13 bit of monotonicity, mathematically demonstrated.

I don't understand what do you mean about the power supplies, you are using linear regulators, while Ian for example offers battery supply to decouple the device from the main AC. Do you know about stray capacitance in transformer when powering digital circuit? I think so.
Maybe you could offer a modular device, like Ian, so the user could decide if lower the cost using standard parts or upgrade the system with a good master clock and maybe battery power supply.

But if are using a R2R DAC capable of great performance (you say) to watch Music Videos on youtube I understand and I give up.
 
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