F4 Beast Builders

If you want to build something, this one has been tested to death and works perfectly. There are certainly other ways to do it that will also work.

How does the output offset behave during warmup? In simulations of the F4 style bias generator, it looked like the output offset was likely to wander during warmup. As a result, I went to using a separate thermistor controlled bias generator for each FET. The basic idea is shown in the schematic:
 

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How does the output offset behave during warmup? In simulations of the F4 style bias generator, it looked like the output offset was likely to wander during warmup. As a result, I went to using a separate thermistor controlled bias generator for each FET. The basic idea is shown in the schematic:

Works perfectly, doesn't drift more than 5mV at start up.

Edit: Let me confirm it. I'm still playing around with the settings. I'll report back. It's certainly below 50mV during warm up. Once it is warmed up, it doesn't go above 1mV.
 
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For those that might be interested, I just checked the resistance setting on the thermal compensation trimpot adjustment. It is reading 3.9k.
If I increase the resistance above this value the bias current goes from high to low and below this value it goes from low to high. Either scenario is still safe and stable.
 
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I changed some values by hearing.....the circuit attached shows the result.

The 147k cascode feedback resistor R40 is good for my pucks, I suppose other pucks will demand slightly different values. The range could be 100k to 180k.

Keep in mind that I do not use the IXYS shown in the Spice but the IXFN48N60P and the IXTN40P50P.

I must use in Spice other types because therefore Spice models exist .

The good news is that the "right" pucks mentioned above, not only sound better but also have at 1W/8 Ohm less distortion than shown in Spice. Look at the picture with the measurement!

Normally Spice values are much lower than reality, but here we have the opposite case!

I suppose the lower capacities at 25V the right ones have, do the job.

I do not get the values Nelsons XA25 manual shows..... but I am very content with the 0.007% I got at 1W/8 Ohm.
Astonishing that despite the low value of distortion the k2 over k3 db difference can be heard nevertheless. Big sound difference between
6db, 10dB and 16dB. Incredible.

And the lateral TO-220 without degeneration and a lower output impedance might help too.
Anyone an idea how low I can go with the gate stopper at the pucks gates?

At the moment I use 100R.

So I got the k2 around 10dB higher than the k2 by ear, seems I start to hear some things..... :)
 

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Generg: You should be able to eliminate degeneration on the laterals and get lower output impedance from the FE. That will require lowering the values of the JFET drain load resistors to get proper biasing. In order to obtain the desired open-loop gain, the resistors in feedback network must also be lowered.
 
The TO220 laterals have around one tenth the transconductance of k2013/j313 so distortion is likely to go up but maybe it might sound better that way.
You could mount the toshiba fets on the main heatsink and increase the bias to a higher level, alternatively how high can you run them on your to220 heatsinks? Why not also work on running k2013 j313 without source resistors.
It can be done. No need to be a scaredy cat. You're abfab membership is dwindling here. :D
Papa limits bandwidth on his Pass Labs amps to a conservative figure. You could probably go lower say 22 Ohms but depending on open loop gain you have, the amp might break away into oscillation. Just drop it to 47 ohms and let yourself decide whether there is an audible improvement.
 
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K2013 and J313 will not thermally run away but they will need to be biased higher.
It's all in the data sheet for your viewing pleasure.

I have already done this before so it certainly is possible. It all comes down to the performance of your heatsinks.
 
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Generg: You should be able to eliminate degeneration on the laterals and get lower output impedance from the FE. That will require lowering the values of the JFET drain load resistors to get proper biasing. In order to obtain the desired open-loop gain, the resistors in feedback network must also be lowered.
Drain resistance at jfets will need to drop significantly for biasing to220 laterals, combined with the lower transconductance of the to220 lateral, open loop gain will come down significantly.
I'd still try it though.
 
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Generg brother, my philosophy is when you can easily find the answer yourself then trust no one but yourself.
You can easily see the behaviour of the raw devices by mounting them on your heatsink and biasing them at 30mA then watch what happens, bias at 50mA then watch what happens, then bias at 100mA and watch what happens etc. The higher you go the less the devices will drift up, especially if you mount them on the main heatsink but maybe that is inconvenient. That is why it really comes down to the performance of your sinks just to keep temperature below say 60C.
I'm referring to doing raw measurements of the devices to characterise their behaviour (not in circuit measurements.)
 
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