From my experience, while it's a good idea to have closely-matched Idss ... I've found the transconductance of Idss-matched JFETs (and therefore the gain they produce) is wildly different. But I don't know if the transconductance of JFETs from the same production batch would be more constant?
Regards,
Andy
Gain confusion
I'm using the DCB1 buffer with a Aleph clone (26 dB gain). I am concerned with having the appropriate/enough gain for a Shure V15 III (3.5mV).
Found this: Taking the Guesswork out of Phonostage Gain | The Absolute Sound
Using the formula, I need 49dB, though the build guide states MM should be 40dB.
Which should I build?
Thanks in advance.
I'm using the DCB1 buffer with a Aleph clone (26 dB gain). I am concerned with having the appropriate/enough gain for a Shure V15 III (3.5mV).
Found this: Taking the Guesswork out of Phonostage Gain | The Absolute Sound
Using the formula, I need 49dB, though the build guide states MM should be 40dB.
Which should I build?
Thanks in advance.
The "I need 49dB" comes from the assumption he makes for 0dBV (1VRMS) when consumer gear is -10dBV standard. CD replay is usually the wild one. Over-amplifying in the phono leads to higher self noise floor and clipping danger in high velocity cuts (peaks). Its wiser to have 10dB of line gain when with less than 90dB SPL/W speakers. You may try "steal" 3dB more for what missing from not having a preamp with gain. I.e. see if you will have clean replay even on your loudest records and 43dB setting since the Shure is not full out 5mV MM, but no more. You will overload the input stage with more. If you will make a mini survey among commercial phonos you will find that the strong majority hovers around the 40dB figure for MM. Better use your volume pot in high settings when with a DCB1 that adds no perceptible hiss itself. Your practical criterion should be getting or not loud enough music at your seat for your listening habits before you run out of volume pot clockwise.
Normally you should have 10-15dB of line pre gain on tap in that system or 95dB speakers, but again, if you will get music loud enough for your habits when turning the knob high and you still prefer the DCB1 quality wise, then you will be covered.
I agree.
It seems from the datasheets that there is considerable variation in the way the production process gives specified parameters.
Matching by Idss alone is not matching in my opinion. It is selecting by Idss.
Matching, to me, means a minimum of two points along the Id vs Vgs curve.
This gives the slope and the value between the two points selected for matching.
I have tested a lot of jFETs, from various manufacturers, in various gm types and over a range of Idss.
jFETs vary enormously. Careful measurement is required where the circuit needs matching of parameters.
In the situation where degeneration brings the operating parameters to within an acceptable range, then matching is not required.
Judging by the comments and suggestions on these Forum, it appears that degeneration does not have that effect of bringing parameters into the acceptable range. Many are reporting sound improvements where devices are selected at various locations and across the two stereo channels.
So which is it?
degeneration solves all the parameters variations and selecting/matching is NOT required
or
selecting/matching is required in some locations to bring operating parameters within tolerable range.
Firstly let's use the correct term you reminded for IDSS picking, when matching is a popular misinforming term. Matching a parameter is not matching devices. IDSS selection it is the proper term then.
In this circuit the IDSS selection is central because its an influential factor in determining the bias current. On those drops the bias current creates on assorted resistive elements we rely centering the input stage especially for proper symmetry and headroom. Also importantly it determines the mW on the JFETs to keep their Tc drifting alike. Even in this low noise stage, the degeneration is 20% on its lightest (LMC) to 80% on its heaviest (MM).
In the second stage the degeneration is 42% across all settings. Keeps the gain multiplier in check.
After testing many alike builds and carefully monitoring the prototype PCB build for what IDSS JFETs went in and putting them through curve tracing first, I have seen that even with bit different gfs samples when IDSS selected to the tolerances given in the guide, it will be difficult to go amiss by more than 0.3dB final channel matching on highest sensitivity setting.
Just because few builders will have tracers or will go into full characterization lengths of JFETs with expert confidence, I had determined that the IDSS selection is practical enough. Even when so, I mentioned FFT testing and R8 trimming for the geared up and experienced lot.
For JFET full matching principles, what you and others mention of course stands true but its more of a general interest matter on JFET properties.
In this circuit the IDSS selection is central because its an influential factor in determining the bias current. On those drops the bias current creates on assorted resistive elements we rely centering the input stage especially for proper symmetry and headroom. Also importantly it determines the mW on the JFETs to keep their Tc drifting alike. Even in this low noise stage, the degeneration is 20% on its lightest (LMC) to 80% on its heaviest (MM).
In the second stage the degeneration is 42% across all settings. Keeps the gain multiplier in check.
After testing many alike builds and carefully monitoring the prototype PCB build for what IDSS JFETs went in and putting them through curve tracing first, I have seen that even with bit different gfs samples when IDSS selected to the tolerances given in the guide, it will be difficult to go amiss by more than 0.3dB final channel matching on highest sensitivity setting.
Just because few builders will have tracers or will go into full characterization lengths of JFETs with expert confidence, I had determined that the IDSS selection is practical enough. Even when so, I mentioned FFT testing and R8 trimming for the geared up and experienced lot.
For JFET full matching principles, what you and others mention of course stands true but its more of a general interest matter on JFET properties.