Drive NOS AD1865/62,PCM1704/02/63,TDA1541 from FIFO: Universal I2S-PCM driver board

[iancanada]

I2S-PCM board uses a simple CPLD not an FPGA and is carefully designed as far as grounding, powering and trace impedances are concerned. I would be happy to say the same about most of the available DAC kits.

All isolators add a fairly large amount of jitter. In Ian's design-stack simply adding an isolator between DAC and I2S-PCM would deceive the whole role of the FIFO which is eliminating jitter.

In order to do what you are suggesting: isolating the I2S-PCM board from the DAC and not shooting yourself in foot with a jittery isolator you would also have to move the clocks and a reclocking stage on the DAC side. Of course these clocks will have to be routed back to the dual-clock board through an isolator. In _my opinion_ this is theoretically possible -even with the current isolator board- but I have high doubts whether you gain anything from it.

Thanks Zsolt for your perfect answer .

Ian,

For lower noise, would not it be better to have 1704 board on FIFO side,
before isolators?

TonyB

Hi TonyB,

1. EPM240T consume only 35mA current @ 98.3040Mhz MCLK & 384KHz Fs, so it's not that bad;
2. There is a Potato GHzTTL FF working at last stage, re-clocking everything by the original MCLK, it will stop any additive jitter from FPGA.
2. FPGA has it's own low noise reg, together with it's own GND plate separated from output stage.

I'm not against you add an additional isolator between the PCM daughter board and DAC, but please keep in mind the key thing is we have to place the original clock at same side of DAC. If you have seen the isolator jitter measurement result, you will agree why I'm always saying: never isolating MCLK from DAC..

Regards,

Ian

 

[hochopeper]

Hi Guglielmo,

Thank you for interesting. There are only 4 signals need to be connected to a DAC, it should be very easy. But I'm sorry, I didn't get what extra PCB you need for your DAC.

Regards,

Ian

Ian,

I think Guglielmo was asking you to design a DAC PCB .

Guglielmo,

I agree it is a nice idea, to have a DAC with similar design approach as Ian has taken with his FIFO designs. Unfortunately with people's DAC preferences Ian would be designing a number of DAC pcbs to cater for everyone's choice in DAC/IV etc. My preference is generally to have the IV very close to the DAC so this presents a challenge where he would end up with an endless list of demands. This was discussed previously and from memory Ian commented he just wasn't interested in doing a DAC design, he lets you make those choices and just gives you the best I2S signal he can at the output of his designs.


Cheers,
Chris

 

[guglielmope]

Hello Chris,
there is no problem about boards, my idea was only to complete the digital path in the correct way, many times we speak about jitter and pseconds and we connect digital segnals with long wires to existing boards ,may be cutting the old tracks of a CS8412 or better.
A analog current output is not a problem and some cm of wire can separate in the better way digital and analog world.
For example an AD1865 adapter board needs only the dac, 3 caps and input/output connections.
Ciao
Guglielmo

 

[pavelal]

Loboone x 1

pavelal x 1
total 97 i think

 

[qusp]

we know what you meant Guglielmo, but the suggestion is that you should do it yourself Ian has left the dac to others for a reason. btw adding longer wires to the IV stage is never an improvement

 

[flowerpot]

TOTAL 97

TV Man x 2
merlin el mago
rtd
jameshillj
erin x1 (or 2)
Nikola Krivorov x1
Rupor54
vitalica
analog_sa
andrea_mori x 5
dsavitsk
tagheuer
hirez69 x 2
ccliu x 2
BDL
cddumat
regal x 2
zoran
Jogi
Zen(zenelectro) x 2
Buzzforb
SPWON
crobbins5421 X 2
marcus1 x1 (or 2)
casshan x 2
Dweeb99 X 2
jackw X 2
kazap X 2
danzup x 3
Giordano x2
Tony_T
Tubo x1
clivem x2
noizas x4
JoeyDD x2
skullaudio
dinos8746 x2
dvb-projekt
bisesik x2
guglielmope x1
Valeriano x1
mhgawel x1
av-trouvaille x 1 (or 2)
iloveswan x1
dtses
Flyboi X1
Lil' Knight x1 (or 2)
skippyboy x1
acccruz x1 (or 2)
WhiteBull x1
hksidney x 1
vts2006 x 3
JustBuildLspkAS.x3 &1 fifo kit finished for pcm1704 (ihave AD1862 ,pcm63,pcm1704)
54: PET-240 2 * TDA1541
TonyB
damohpi x1
iloveswan x 1
Joseph K x 2
mefistofelez x2 (pcm63P)
JLOP x1 (WaveIO, AD1865 NOS SRPP)
sceglar x1
4me2ctv x 1
tubesguy x 1
ctrange x 1
spm x 1
Joonas x1
Loboone x 1
flowerpot x 1

 

[pavelal]

Total 97 already was before, two message before, now 98 i think:

TOTAL 98

TV Man x 2
merlin el mago
rtd
jameshillj
erin x1 (or 2)
Nikola Krivorov x1
Rupor54
vitalica
analog_sa
andrea_mori x 5
dsavitsk
tagheuer
hirez69 x 2
ccliu x 2
BDL
cddumat
regal x 2
zoran
Jogi
Zen(zenelectro) x 2
Buzzforb
SPWON
crobbins5421 X 2
marcus1 x1 (or 2)
casshan x 2
Dweeb99 X 2
jackw X 2
kazap X 2
danzup x 3
Giordano x2
Tony_T
Tubo x1
clivem x2
noizas x4
JoeyDD x2
skullaudio
dinos8746 x2
dvb-projekt
bisesik x2
guglielmope x1
Valeriano x1
mhgawel x1
av-trouvaille x 1 (or 2)
iloveswan x1
dtses
Flyboi X1
Lil' Knight x1 (or 2)
skippyboy x1
acccruz x1 (or 2)
WhiteBull x1
hksidney x 1
vts2006 x 3
JustBuildLspkAS.x3 &1 fifo kit finished for pcm1704 (ihave AD1862 ,pcm63,pcm1704)
54: PET-240 2 * TDA1541
TonyB
damohpi x1
iloveswan x 1
Joseph K x 2
mefistofelez x2 (pcm63P)
JLOP x1 (WaveIO, AD1865 NOS SRPP)
sceglar x1
4me2ctv x 1
tubesguy x 1
ctrange x 1
spm x 1
Joonas x1
Loboone x 1
flowerpot x 1
pavelal x 1

 

[flowerpot]

Hi Ian,

Do we still have double CLK abd LLLR outputs ? Is it on U.FL sockets ? Or will be through PH2.0 cable ?

I am designing the DAC PCB to align the DAC inputs to the DB outputs and also to go dual mono or not... Thanks

PCB design revised once again

1. Layout was optimized for low noise and transition line impendence matching
2. Double CLK and LLLR outputs for dual mono DACs
3. Enhanced power supply layout available for both on board low noise LDO and external high quality PSU
4. Additional DC output connector position for powering the possible I2S isolator

Please let me know for any comment.

Ian

 

[Steve Ha]

TOTAL 99

TV Man x 2
merlin el mago
rtd
jameshillj
erin x1 (or 2)
Nikola Krivorov x1
Rupor54
vitalica
analog_sa
andrea_mori x 5
dsavitsk
tagheuer
hirez69 x 2
ccliu x 2
BDL
cddumat
regal x 2
zoran
Jogi
Zen(zenelectro) x 2
Buzzforb
SPWON
crobbins5421 X 2
marcus1 x1 (or 2)
casshan x 2
Dweeb99 X 2
jackw X 2
kazap X 2
danzup x 3
Giordano x2
Tony_T
Tubo x1
clivem x2
noizas x4
JoeyDD x2
skullaudio
dinos8746 x2
dvb-projekt
bisesik x2
guglielmope x1
Valeriano x1
mhgawel x1
av-trouvaille x 1 (or 2)
iloveswan x1
dtses
Flyboi X1
Lil' Knight x1 (or 2)
skippyboy x1
acccruz x1 (or 2)
WhiteBull x1
hksidney x 1
vts2006 x 3
JustBuildLspkAS.x3 &1 fifo kit finished for pcm1704 (ihave AD1862 ,pcm63,pcm1704)
54: PET-240 2 * TDA1541
TonyB
damohpi x1
iloveswan x 1
Joseph K x 2
mefistofelez x2 (pcm63P)
JLOP x1 (WaveIO, AD1865 NOS SRPP)
sceglar x1
4me2ctv x 1
tubesguy x 1
ctrange x 1
spm x 1
Joonas x1
Loboone x 1
flowerpot x 1
pavelal x 1
Steve Ha x 1

 

[pavelal]

Hi all
maybe someone knows if DB is compatible with PCM63, considering the specifics of such a PCM63?:
"“Stopped Clock” Operation
The PCM63P is normally operated with a continuous clock
input signal. If the clock is to be stopped between input data
words, the last 20 bits shifted in are not actually shifted from
the serial register to the latched parallel DAC register until
Latch Enable (LE, P20) goes low. Latch Enable must remain
low until after the first clock cycle of the next data word
to insure proper DAC operation."
I have not seen before that someone wrote about trying to build a DAC PCM63 on the board DB

And other question - how would be correct to connect the DB board with FIFO if I need to use the digital output on the SPDIF board?

Thanks

 

[new2hifi]

100

TOTAL 100

TV Man x 2
merlin el mago
rtd
jameshillj
erin x1 (or 2)
Nikola Krivorov x1
Rupor54
vitalica
analog_sa
andrea_mori x 5
dsavitsk
tagheuer
hirez69 x 2
ccliu x 2
BDL
cddumat
regal x 2
zoran
Jogi
Zen(zenelectro) x 2
Buzzforb
SPWON
crobbins5421 X 2
marcus1 x1 (or 2)
casshan x 2
Dweeb99 X 2
jackw X 2
kazap X 2
danzup x 3
Giordano x2
Tony_T
Tubo x1
clivem x2
noizas x4
JoeyDD x2
skullaudio
dinos8746 x2
dvb-projekt
bisesik x2
guglielmope x1
Valeriano x1
mhgawel x1
av-trouvaille x 1 (or 2)
iloveswan x1
dtses
Flyboi X1
Lil' Knight x1 (or 2)
skippyboy x1
acccruz x1 (or 2)
WhiteBull x1
hksidney x 1
vts2006 x 3
JustBuildLspkAS.x3 &1 fifo kit finished for pcm1704 (ihave AD1862 ,pcm63,pcm1704)
54: PET-240 2 * TDA1541
TonyB
damohpi x1
iloveswan x 1
Joseph K x 2
mefistofelez x2 (pcm63P)
JLOP x1 (WaveIO, AD1865 NOS SRPP)
sceglar x1
4me2ctv x 1
tubesguy x 1
ctrange x 1
spm x 1
Joonas x1
Loboone x 1
flowerpot x 1
pavelal x 1
Steve Ha x 1
new2hifi x 1

 

[Superdad]

Pardon my ignorance, I am new to participating in group buys:
1) When does the current group buy close?
2) When do the boards get made?
3) Who and when do I pay--and who takes my address and mails the board?

Also, I can not recall the price and shipping charges for the I2S>PCM board. Once someone provides the answers to the above, I will happily add my name to the list.
Thanks,
ALEX

 

[hochopeper]

Pardon my ignorance, I am new to participating in group buys:
1) When does the current group buy close?
2) When do the boards get made?
3) Who and when do I pay--and who takes my address and mails the board?

Also, I can not recall the price and shipping charges for the I2S>PCM board. Once someone provides the answers to the above, I will happily add my name to the list.
Thanks,
ALEX

This thread is actually not a GB as such, the list is registering interest in a design that iancanada is working on and has prototyped. By registering interest Ian can gauge interest and work out if there is sufficient interest to run a GB at all, the set up cost to manufacture these things is significant and as a hobby, not at all viable for short runs. The design here is quite unique and there is no equivalent that I'm aware of.

To answer your questions:
1) there is no end date to the list, when Ian is ready and when he is satisfied there is sufficient interest, then he'll make that known.
2) See above
3) Who: Ian, When: when he asks

 

[Superdad]

This thread is actually not a GB as such, the list is registering interest in a design that iancanada is working on and has prototyped. By registering interest Ian can gauge interest and work out if there is sufficient interest to run a GB at all, the set up cost to manufacture these things is significant and as a hobby, not at all viable for short runs. The design here is quite unique and there is no equivalent that I'm aware of.

Thanks for the quick reply. Gee, with a 100 boards of interest already registered (101 when I update the list in a moment), it would seem a ready and viable time to go into production. Bittele in Ontario will run fewer that that at a very reasonable price. I'm ready to buy and don't particularly wish to wait another 6 months.
Judging by Ian's pics on the first post, the design looks pretty ready to bake!

 

[Superdad]

101 !!

TOTAL 101

TV Man x 2
merlin el mago
rtd
jameshillj
erin x1 (or 2)
Nikola Krivorov x1
Rupor54
vitalica
analog_sa
andrea_mori x 5
dsavitsk
tagheuer
hirez69 x 2
ccliu x 2
BDL
cddumat
regal x 2
zoran
Jogi
Zen(zenelectro) x 2
Buzzforb
SPWON
crobbins5421 X 2
marcus1 x1 (or 2)
casshan x 2
Dweeb99 X 2
jackw X 2
kazap X 2
danzup x 3
Giordano x2
Tony_T
Tubo x1
clivem x2
noizas x4
JoeyDD x2
skullaudio
dinos8746 x2
dvb-projekt
bisesik x2
guglielmope x1
Valeriano x1
mhgawel x1
av-trouvaille x 1 (or 2)
iloveswan x1
dtses
Flyboi X1
Lil' Knight x1 (or 2)
skippyboy x1
acccruz x1 (or 2)
WhiteBull x1
hksidney x 1
vts2006 x 3
JustBuildLspkAS.x3 &1 fifo kit finished for pcm1704 (ihave AD1862 ,pcm63,pcm1704)
54: PET-240 2 * TDA1541
TonyB
damohpi x1
iloveswan x 1
Joseph K x 2
mefistofelez x2 (pcm63P)
JLOP x1 (WaveIO, AD1865 NOS SRPP)
sceglar x1
4me2ctv x 1
tubesguy x 1
ctrange x 1
spm x 1
Joonas x1
Loboone x 1
flowerpot x 1
pavelal x 1
Steve Ha x 1
new2hifi x 1
Superdad x 1 (WaveIO, PCM1704K, discrete I/V)

 

[hochopeper]

Thanks for the quick reply. Gee, with a 100 boards of interest already registered (101 when I update the list in a moment), it would seem a ready and viable time to go into production. Bittele in Ontario will run fewer that that at a very reasonable price. I'm ready to buy and don't particularly wish to wait another 6 months.
Judging by Ian's pics on the first post, the design looks pretty ready to bake!

I think hardware is pretty right, its software that's needed to be tested and make sure it works with all the different clocking schemes necessary to meet the demands of everyone Ian won't release something half-done and he's also been on a 1 month holiday earlier in the year and has mentioned in one of his threads that he had a busy month or so coming up at work. This is a hobby project of his so I think we need to remember that this is not a commercial endeavour and his personal time is only finite.

 

[vzs]

AD1865 & AD1862 352.8/384KHz issue?

Hi,

According to timing requirements AD1865 and AD1862 are capable to handle clocks up to 13.5MHz (pulse cycle >74ns) and 17MHz (pulse cycle >60ns). TI DACs do well up to 25MHz.

The current I2S-PCM board CLK follows the SCK frequency from I2S which means that for 352.8/384KHz materials the CLK will be 22.5792/24.576MHz.

The FIFO as most I2S sources use 64Fs I2S format. The serial I2S stream is converted by the I2S-PCM board into two, parallel, MSB first streams so theoretically half the speed of the incoming I2S SCK is enough to transfer the converted streams.

With an half-speed CLK mode AD1865 and AD1862 could enjoy 352.8/384KHz materials as well.

Ian reviewed this issue and said it might be possible to fit this feature into the CPLD but he cannot decide if he needs to do it before the group buy. This might postpone the whole group buy.

The question is: how many from the GB list with AD1865/AD1862 would like to use 352.8/384KHz materials?

Ian, if you decide to add this feature, is it possible to upgrade the software of those who need it later?

Thanks,
Zsolt

 

[iancanada]

Optional half-speed mode for ADS1865/62 running at 384KHz

Hi,

According to timing requirements AD1865 and AD1862 are capable to handle clocks up to 13.5MHz (pulse cycle >74ns) and 17MHz (pulse cycle >60ns). TI DACs do well up to 25MHz.

The current I2S-PCM board CLK follows the SCK frequency from I2S which means that for 352.8/384KHz materials the CLK will be 22.5792/24.576MHz.

The FIFO as most I2S sources use 64Fs I2S format. The serial I2S stream is converted by the I2S-PCM board into two, parallel, MSB first streams so theoretically half the speed of the incoming I2S SCK is enough to transfer the converted streams.

With an half-speed CLK mode AD1865 and AD1862 could enjoy 352.8/384KHz materials as well.

Ian reviewed this issue and said it might be possible to fit this feature into the CPLD but he cannot decide if he needs to do it before the group buy. This might postpone the whole group buy.

The question is: how many from the GB list with AD1865/AD1862 would like to use 352.8/384KHz materials?

Ian, if you decide to add this feature, is it possible to upgrade the software of those who need it later?

Thanks,
Zsolt

Thank you so much Zsolt, you found a very significant issue just before I release it.

I designed a test fixture and confirmed that the PCM daughter board was running bit perfect throughout 44.1 KHz to 384 KHz. But I didn’t notice that the max CLK frequency of AD1865/AD1862 was just 13.5/17MHz.

In current design, the CLK signal of PCM output follows the SCK frequency of I2S input. That means with 64Fs I2S input, the CLK frequency will be 22.579/24.576 MHz at 352/384KHz Fs. According to the datasheet, AD1865/AD1862 can’t work at this frequency, which is just 8*44.1/48KHz .

I did some review on the verilog code and found a possible solution. The CPLD architecture I designed has two main modules with independent from each other. One is the I2S receiver, the other is the PCM transmitter. And fortunately I placed a pair of buffers between them for both left and right data (not just a shift register ), that similar to the FIFO but in sync mode. If I open a new half-speed jumper to control PCM output CLK running at SCK or optional SCK/2, the problem will be solved. It can also be a flexible CLK option for PCM DACs other than AD1865/62

I’ll start doing some simulation. It won’t be difficult to implement if it can pass the simulation.

I already ordered the final PCB, as well as the BOM. The above changes will be just related to the verilog code and has nothing to do with the hardware. So, it will not slow down the GB. I’m trying to run it as soon as possible.

Have a nice weekend.

Ian

 

[new2hifi]

...........In current design, the CLK signal of PCM output follows the SCK frequency of I2S input. That means with 64Fs I2S input, the CLK frequency will be 22.579/24.576 MHz at 352/384KHz Fs. ..........Ian

Ok! Now I am confused. TI PCM1704 can do 24bit/768kHz as per datasheet (page 7) with 32-bit frame length, thus meeting the maximum BCLK rate of 24.576MHz (32 x 768).

I am confused that why this converter uses 64-bit frame length?

 

[qusp]

perhaps its because there is not a single interface that can output 768kHz i2s/PCM afaik (see edit, there are a couple), there is no native 768khz PCM content available and even if there was it would be upsampled and somewhat pointless? the inherent LPF in the vast majority of amplifiers and line stages, even if its just gate capacitance of devices used, renders this content as noise only. not really a possible feature that should impose changes on hardware or software IMO.

just because you can do something, does not mean that you should. THD, noise and other performance will in most cases be significantly worse at 768khz (somePWM and class D noise and harmonics are the same independent of frequency), most DACS perform at their best at 96-192khz. then of course there is the lack of a 768khz ADC. the 768khz ability is driven by marketing, there are probably companies selling $500-1000 firmware upgrades to supply such a possibility.

actually I lie, the Zodiac platinum will do it over USB, there is probably a couple of other proprietary very expensive products with custom drivers that can, just so they are able to justify an 'upgrade' to previous versions and have more exclusive buzzwords. the rest of my post stands.