It will be going toe to toe with TSSA and some Firstwatt stuff
Excellent, full report follows, I asume.
Some of the recent posts about the 2200 uFd cap rating, and the bias current started me thinking (not always a good thing, I admit), so I built the circuit on a little breadboard. I basically wanted to see how the VAS bias current with CCS behaves over normal changes in rail voltage and temperature, compared to using a 15K resistor.
Everything worked as described by LC and others in previous posts, I adjusted the current to 2.4 mA with a trimpot, voltage at the 2200 cap was around 0.84V, offset adjusted close to zero, all good... Voltage at the 2200 cap measures around 0.85V, VAS bias around 13-14 mA. (the JFET I am using for testing is a Fairchild BF244B, it takes under 1K series resistance to get 2.4mA out)
However, as best as I can tell, with 40V rails, the voltage in my circuit exceeds the maximum for a 30V JFET (like the BF545B specified in the BOM). So, am I missing something, or not reading the p/n in the BOM correctly...?
Everything worked as described by LC and others in previous posts, I adjusted the current to 2.4 mA with a trimpot, voltage at the 2200 cap was around 0.84V, offset adjusted close to zero, all good... Voltage at the 2200 cap measures around 0.85V, VAS bias around 13-14 mA. (the JFET I am using for testing is a Fairchild BF244B, it takes under 1K series resistance to get 2.4mA out)
However, as best as I can tell, with 40V rails, the voltage in my circuit exceeds the maximum for a 30V JFET (like the BF545B specified in the BOM). So, am I missing something, or not reading the p/n in the BOM correctly...?
Ok, got that, so my test was valid, I was just wondering if I missed something as usual... there should be a self-editing feature to these threads!
There are several people who built the through-hole version starting from Shaan's schematic, in the Pee-Cee-Bee thread, all with good independent feedback.
I would be the first to admit that a circuit you design/build yourself will benefit from your own subjective bias, but most of us who posted there have had nothing to do with the actual design, just the build part, and most have come to this architecture fresh, and did not participate in the previous SSA threads. (with the exception of Shaan)
Also, the boards in the PeeCeeBee thread were all built with conventional parts, and without most of the refinements in the later versions of the VSSA circuit, so LC's boards can only sound better, if you take my point.
@Trunek: I measured some very decent slew rate numbers, with the through-hole boards, even with an input filter, and using "safe" component selection for some of the critical parts, and posted the results here (post #335, pic #9, measured with a real speaker load and about 10 feet of speaker wire):
http://www.diyaudio.com/forums/solid-state/231662-peeceebee-34.html#post3484146
Again, with more optimum component selection LC's boards can only perform better.
Yes, did not mean to imply anything else, just poor choice of words on my part. The point should have been that if someone is looking for a reason/reassurance, there is plenty in that thread from happy customers...VSSA SMD was made, tested and listened to, long before Shaan's version. He strictly follows first post of this thread (without CCSs).
@supernet
Your ERSA works nicely.
BTW nice tablecloth.
@meanman1964
wait for the first comments of VSSA GB recepients, deliveries just started
I-CON or I-CON NANO?
First VSSA batch for 14 recipients sent out today. Hopefully everyone will get it soon.
Let the fun begin boys.
I can see my name on the top : that's good
Less than 50ns 10V P-P into 50Ω http://www.teknetelectronics.com/DataSheet/WAVETEK/WAVET_182A_188110658.pdf