500v/uS slewrate, really?

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Neutrality

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Joined 2004
Doing some simulation with a complementary JFET input stage using 2SK246/2SJ103, instead of the usually recommended 2SK170/2SJ74 JFETs.

Mostly for fun and to see what I could get out of it.

Was a little amazed at the insane slewrate I could achieve and still maintain a nice looking 20 KHz squarewave and good phase and gain margins.

Only downside is THD-20 that is around 0.02% at 60 Watt, 8 Ohm load, the 1 W 8 Ohm load THD-20 is a more decent 0.001XXX%.

THD-1 1 W, 8 Ohm load is 0.0002XXX% rising to 0.0017XX% at 60 W, 8 Ohm load.
 

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jcx

Member
Joined 2003
yes it is literally unbelievable

try setting the sim max step size time in your sim to something appropriate to such an edge - like 1 nS

also look at driver bias, output shoot thru - I don't think that 120 Ohm resistor can drain the output Mosfet gate charge that fast
 
R

RJM1

Member
Joined 2010
To measure the slew rate of an amplifier you measure the rise and fall times of a pulse waveform. Rise time is measured from 10% above the minimum voltage to 90% of the maximum voltage and fall time is measured from 10% below the maximum voltage to 90% of the minimum voltage. If you are measuring a square wave output of an amplifier the 10 and 90% points should be of equal voltage and opposite polarity
The rising slew rate that you measured in your first post (pic #2) was between -31.33 and 20.3 Volts and the falling slew rate (pic #3) were between 33.97 and -16.11 Volts.
It’s easy to get insane slew rates when you throw out the slower parts of the signal.
 
tiefbassuebertr

tiefbassuebertr

Member
Joined 2005
tiefbassuebertragung.de
Bonsai said:
The question here is does your simulation in this case represent the real world? 5pf Cdom seems a bit low to me.
Click to expand...
A great issue by simulation are the not present parasitic components from real world. An example is the capacitor parallel to the NFB resistor, that is connected between tje output and the inverted input. By various commercial amps this capacitor exist not as a component, but neverthless this capatitor is present (in the aera between 10pF and 50pF, independend from the posotion of the copper-wires from the PCB).
By a power amp example from the German brand MERACUS, that I have get for re-design (causes unwanted oscillation), I measure a value about 30pF.
This means for me, in the circuit for simulation one must actually introduce all values for existing virtual capacitors and inductors, which result from the PCB trace routing (at least the most important parasitic devices).
Unfortunately a great challenge.
Because most engineers does that, CAD for audio amps has a very bad call - see various comments towards the end about
http://www.diyaudio.com/forums/solid-state/89023-bob-cordell-interview-error-correction.html
 
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A

AndrewT

R.I.P.
Joined 2004
I tried WikiP, but I did not find it.

Taking the slew rate time period at 90% of the signal change, rings a bell.
Could it be from 5% to 95%, i.e. 90% of the whole signal change or as stated earlier 10% to 90% for an effective 80% of the whole signal change.

Can some/many confirm?
 
Lazy Cat

Lazy Cat

Member
Joined 2007
I think Tektronix measuring equipment company knows something about this simple question. :)

Look to my Tek plot of 1 kHz square wave and you will see that it starts to measure slew rate from 10% to 90% of the signal Vpp (rise time). Also you can readout the same value from the plot itself or from the right side value result (80% of 138Vpp in 448ns rise time). ;)
 
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