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...i've made up my mind that dc offset above 10mV and capacitor in feedback is a sign of a bad design.
Then you won't like my amplifiers, they're all bad designs
I am speaking reasonable good coupling C against NONE at all.
About having done the experiment, I am a (really) poorly hear gifted engineer, so I must believe what I can instrumentally measure and demonstrate. Having better "sonics" without any number for me is meaningless, I am sorry. And I want to see how many of the so called golden heared converge to the same solution in a blind test. I believe that "sonics" is not only highly subjective, but even not time-invariant .
Signal distorsion by various capacitor types is well documented. Try documents attacthed to post 8448 here:
http://www.diyaudio.com/forums/anal...curls-blowtorch-preamplifier-part-ii-845.html
Obviously some caps are better then others. The question is when a cap is good enough for audio signal coupling. Apparently for ultimate grade equipment such capacitor is neither cheap nor small, so avoiding caps by using JFET input stage can be good idea.
One could also question spectral content of the BJT distionsions vs JFET distiorsions.
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But if you don't use a CCS like me then the LTP current and it's balance varies with supply voltage. On the other hand, I don't strive for the ultra-low dc offsets that some people seem so keen on around here...
Huh? A CCS has nothing to do with DC offset.
Im lucky to get below 50mV. And i've made up my mind that dc offset above 10mV and capacitor in feedback is a sign of a bad design.
Low DC offset is a good sign that you are doing things correctly. Block DC on input and reduce DC gain to zero are the big ones.
One reason why you may want a cap in the input is when you can't guarantee the nature of the source.
Very true for commercial amplifiers. Not required for DIY geeks well aware of line sources in their domestic systems.
I like this one and certainly cannot disagree.Low DC offset is a good sign that you are doing things correctly.
I would never deliberately unbalance an LTP by adding VR to either the collectors or to the emitters.
If the input to the +IN of the LTP is zero and the devices are matched and have matched loadings and pass the same currents then the output offset of the LTP is also zero.
If the LTP devices are thermally coupled, matched as above and dissipate the same heat, then the output offset remains at zero with sensible changes in Ta.
I cannot agree with this "head in the sand" philosophy, but then all regular readers know my reputation for playing safe.Not required for DIY geeks well aware of line sources in their domestic systems.
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Huh? A CCS has nothing to do with DC offset.
You can unbalance an LTP by changing the tail current. A CCS tends to avoid that.
I don't see any merit in insisting on 10mV or less of offset other than it's possible. What's wrong with 50mV of offset ?
I've noticed that none of my diy amps with a capacitor in the feedback loop with dc gain at 0 have anywhere near as good bass response as the commercial dc coupled telefunken amp which is the best sounding amp i own.
None of my diy builds so far come nowhere close.
Anyways heres something i came up with, in simulation it does indeed work to null dc offset with a pot in the ccs:
None of my diy builds so far come nowhere close.
Anyways heres something i came up with, in simulation it does indeed work to null dc offset with a pot in the ccs:
it must be a fluke, or you asked the simulator the wrong question.Anyways heres something i came up with, in simulation it does indeed work to null dc offset with a pot in the ccs:
The simulator will select the LTP to have input offset current exactly equal.
The input offset voltage cannot be zero with the difference in +IN & -IN loadings shown.
Therefore an apparent output offset correction must be a fluke.
However, if J1 is presented with a source resistance of 1k0, to match r15, then input offset voltage is zero.
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You can unbalance an LTP by changing the tail current. A CCS tends to avoid that.
There is a whole list of things to intentionally unbalance the LTP - don't do them!
Using an active CCS has its advantages over using just a resistor but LTP balance isn't one of them. You need a design amount of current through the LTP, whatever way you get it should not affect LTP balance - not by any significant amount.
which reminds me:
varying the value of r10 varies the VAS Ic current.
This will vary the current injected into the collector of Q2.
That can be used to ensure exactly equal Vdrop across R3 & R4. Balance of LTP achieved.
However, if J1 is presented with a source resistance of 1k0, to match r15, then input offset voltage is zero.
Yes! Do this! Put a 1k0 in series between J1 and R8 to balance the DC input voltages due to standing base currents.
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