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Old 29th September 2021, 07:59 PM   #2311
TimCurtis is online now TimCurtis  United States
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Location: Metro-Detroit
Ok, just let me know ahead of release if kernel bump or driver compile is needed so I can get those into the build process :-)
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Old 13th October 2021, 04:01 PM   #2312
chris14 is offline chris14
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Join Date: Jan 2018
Originally Posted by cdsgames View Post

sorry been out with the flu .
For the AMP I hope that next week I can show some pics. AMP and buffer (preamp) is final . PSU is working but I need to incorporate the changes/mods into new PCB . Not a big deal
Digione Sig 2 and USBridge 4 , depends on components shortage for mass production . The new PCB , proto of DS2 , should arrive this week.
On this generaton , we have used a 8 super-regulators (discreet ) powering Xtals , buffers and flipflops , basically anywhere that SPDIF signal is present . Clocks are based on Andrea Mori design (so we used our own xtal , proudly made in Canada) with our own sinewave and squarer ICs.

Usbridge4 ...we also used superregulators and our own Xtals for the USB clock .
Understand that timing of production is dependent upon component availability, but is there any more detail/results that you can share on the Amp & buffer?
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Old 15th October 2021, 09:07 AM   #2313
surfer2010 is offline surfer2010
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Default Revolution with Optical TOSLINK (SPDIF) input?


are there any plans to implement an Optical TOSLINK (SPDIF) input for the Revolution DAC?

this would be very helpful for us.

Please let us know.


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Old 15th October 2021, 03:34 PM   #2314
Markw4 is offline Markw4  United States
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Join Date: Jul 2016
Location: California
TOSLINK/SPDIF are harder to implement well as compared to asynchronous USB. The reason is that such USB designs can be made fully synchronous with the dac clock while maintaining bit-perfect data integrity.

For TOSLINK/SPDIF type inputs there is another clock at the source end that is not synchronous with the dac clock. Dealing with that requires ASRC or else a FIFO. ASRC resamples the data, and cannot fully remove all incoming jitter. FIFO introduces a time delay and usually requires special programming of an FPGA. The above types of considerations increase dac cost and complexity.
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