Maybe you should study the datasheet. It states that 10uF ceramic is the minimum output capacitance for stability.
Also this should explain why larger capacitors (e.g. elkos) do not work:
As a developer working on LDOVR boards, I can confirm the necessity of the output capacitor to ensure stability. Insufficient capacitance can lead to ringing and introduce output noise (although the correct output voltage may still be maintained). However, the required capacitance is also contingent on the output voltage. Lower output voltages can function with reduced output capacitance. Based on our experiences, LT3045-based boards with 10uF XR7 output caps (Murata GRM series) haven't encountered issues. Nevertheless, if the output voltage is below 5V, a lower output capacitance may suffice. Additionally, it's worth noting that larger output capacitors do not pose any adverse effects.
And that might be the root cause... never parallel differently sized low ESR ceramics when there is any trace inductance. The local 100nF will form a tank circuit with the inductance to the main cap, with the peak often located in the 10Mhz region and the impedance rising to several ohms. Pulse current on the 100nF -- like from Vref of an AK4493 -- will excite the tank circuit exactly at those frequencies.
For LT3045 series, I tend to use one single distributed and augmented plane capacitance. That is, a good dozen of 1uF 0603's caps stitching together the continuous 35µm GND and POWER planes evenly over the whole area and of course always directly at the consumer devices and the regulator. Both the regulator and all the consumer devices will see a very low inductance and low-ESR capacitance with zero ringing. Preferable the regulator is located near the center of the plane and near the most sensitive consumer(s).
You lost me on that one. What does "distributed and augmented plane capacitance" mean?
Where do you find space to parallel 12 ceramic caps? Or do you mean stacking?
I usually put the regulator on little feet next to the to be supplied chip. The LT3045 boards are just 25mm X 50mm.
Maybe I should take off the output cap on the boards and just use the Silmic II on the dac board and do likewise with the OPA1656.
Greets Klaus
Where do you find space to parallel 12 ceramic caps? Or do you mean stacking?
I usually put the regulator on little feet next to the to be supplied chip. The LT3045 boards are just 25mm X 50mm.
Maybe I should take off the output cap on the boards and just use the Silmic II on the dac board and do likewise with the OPA1656.
Greets Klaus
Say you have two DAC chips and one ADC on a PCB. For economic reason you might want to use one single 3.3V regulator to provide power to all the Vref's, the oscillators etc. Then a good power + GND plane design is the natural choice to distribute the supply voltage as it already forms a high speed capacitor notably when there is only a thin pre-preg between the copper layers for the planes.
And this basic plane capacitor can be made much larger and more effective by adding lots of stitching capacitors evenly distributed and at the hot spots, all equal size and type. A dozen or so of 1uF/25V 0603-sized caps don't take up too much board space, IMHO.
When you measure the supply impedances right at regulator, the DAC (or whatever) chips etc you'll find almost textbook-perfect behavior, assuming a decent layout (wrt vias, 35um copper inner layers etc). The nice thing is that the power plane now also is a perfectly valid RF GND plane, albeit with a DC offset. Think of it as a DC level-shifted but otherwise perfect GND plane for RF return currents.