• These commercial threads are for private transactions. diyAudio.com provides these forums for the convenience of our members, but makes no warranty nor assumes any responsibility. We do not vet any members, use of this facility is at your own risk. Customers can post any issues in those threads as long as it is done in a civil manner. All diyAudio rules about conduct apply and will be enforced.

Reference DAC Module - Discrete R-2R Sign Magnitude 24 bit 384 KHz

Since the last firmware update I have a problem with Pauls latest filters. F7 does not load (I get F6 but with the FIR2 corrsponding to F7, i.e. F11).
Before the firmware update I did not had this problem. I reloaded the filters, did a power cycle .... no change.
Code:
F4


dam1021 uManager Rev 0.99  20150817  FPGA Rev 0.99  Press ? for help.

# filters

04 EQHQv5, 192.0 Khz, 0-30.00Khz +-0.00000025dB, 76.80Khz -165.70dB
08 EQHQv5, 384.0 Khz, 0-30.00Khz +-0.00000029dB, 307.20Khz -164.19dB
29 DC Blocking IIR, 384 Ksps, 2 Hz HP 1st order
30 Deemphasis IIR, 384 Ksps, 50/15 uS

# exit


F5


dam1021 uManager Rev 0.99  20150817  FPGA Rev 0.99  Press ? for help.

# filters

05 EQHQ_Apo, 192.0 Khz, 0-20.23Khz +-0.00000019dB, 86.40Khz -168.00dB
09 EQHQ_Apo, 384.0 Khz, 0-20.22Khz +-0.00000012dB, 297.60Khz -171.80dB
29 DC Blocking IIR, 384 Ksps, 2 Hz HP 1st order
30 Deemphasis IIR, 384 Ksps, 50/15 uS


# exit

F6


dam1021 uManager Rev 0.99  20150817  FPGA Rev 0.99  Press ? for help.

# filters

06 Low_Delay_v4, 192.0 Khz, 0-20.00Khz +-0.00000944dB, 76.80Khz -120.50dB
10 Low_Delay_v4, 384.0 Khz, 0-20.00Khz +-0.00000803dB, 313.44Khz -121.91dB
29 DC Blocking IIR, 384 Ksps, 2 Hz HP 1st order
30 Deemphasis IIR, 384 Ksps, 50/15 uS

# exit

F7


dam1021 uManager Rev 0.99  20150817  FPGA Rev 0.99  Press ? for help.

# filters

06 Low_Delay_v4, 192.0 Khz, 0-20.00Khz +-0.00000944dB, 76.80Khz -120.50dB
11 NewNOS, 384 Khz Samplerate Bypass
29 DC Blocking IIR, 384 Ksps, 2 Hz HP 1st order
30 Deemphasis IIR, 384 Ksps, 50/15 uS
 
Works here, did you remember to 'update' after uploading the full image?

# exit

F7


dam1021 uManager Rev 0.99 20150817 FPGA Rev 0.99 Press ? for help.

# filters

07 NewNOS, 44.1Khz Samplerate
11 NewNOS, 352 Khz Samplerate Bypass
29 DC Blocking IIR, 352.8 Ksps, 2 Hz HP 1st order
30 Deemphasis IIR, 352.8 Ksps, 50/15 uS

#
 
Not sure what I did wrong. Reinstalled latest firmware and filters multiple times, but could not change filter.

F4


dam1021 uManager Rev 0.99 20150814 FPGA Rev 0.99 Press ? for help.

# filters

04 Bypass FIR1, 352.8 Ksps
08 Linear Phase FIR2, 352.8 Ksps, 0-83 Khz -1 db, 209 Khz -100 db
29 DC Blocking IIR, 352.8 Ksps, 2 Hz HP 1st order
30 Deemphasis IIR, 352.8 Ksps, 50/15 uS

# exit

F5


dam1021 uManager Rev 0.99 20150814 FPGA Rev 0.99 Press ? for help.

# filters

04 Bypass FIR1, 352.8 Ksps
08 Linear Phase FIR2, 352.8 Ksps, 0-83 Khz -1 db, 209 Khz -100 db
29 DC Blocking IIR, 352.8 Ksps, 2 Hz HP 1st order
30 Deemphasis IIR, 352.8 Ksps, 50/15 uS

# exit

F6


dam1021 uManager Rev 0.99 20150814 FPGA Rev 0.99 Press ? for help.

# filters

04 Bypass FIR1, 352.8 Ksps
08 Linear Phase FIR2, 352.8 Ksps, 0-83 Khz -1 db, 209 Khz -100 db
29 DC Blocking IIR, 352.8 Ksps, 2 Hz HP 1st order
30 Deemphasis IIR, 352.8 Ksps, 50/15 uS

# exit

F7


dam1021 uManager Rev 0.99 20150814 FPGA Rev 0.99 Press ? for help.

# filters

04 Bypass FIR1, 352.8 Ksps
08 Linear Phase FIR2, 352.8 Ksps, 0-83 Khz -1 db, 209 Khz -100 db
29 DC Blocking IIR, 352.8 Ksps, 2 Hz HP 1st order
30 Deemphasis IIR, 352.8 Ksps, 50/15 uS
 
same problems with both 8/14/2015 and 8/17/2015 firmware:

# update
uManager Firmware Update, are you sure ? Updated, resetting.

R0.99
I3
F5
V+00
I3
I0
L352


dam1021 uManager Rev 0.99 20150817 FPGA Rev 0.99 Press ? for help.

# exit

F4


dam1021 uManager Rev 0.99 20150817 FPGA Rev 0.99 Press ? for help.

# filters

04 Bypass FIR1, 352.8 Ksps
08 Linear Phase FIR2, 352.8 Ksps, 0-83 Khz -1 db, 209 Khz -100 db
29 DC Blocking IIR, 352.8 Ksps, 2 Hz HP 1st order
30 Deemphasis IIR, 352.8 Ksps, 50/15 uS

# exit

F5


dam1021 uManager Rev 0.99 20150817 FPGA Rev 0.99 Press ? for help.

# filters

04 Bypass FIR1, 352.8 Ksps
08 Linear Phase FIR2, 352.8 Ksps, 0-83 Khz -1 db, 209 Khz -100 db
29 DC Blocking IIR, 352.8 Ksps, 2 Hz HP 1st order
30 Deemphasis IIR, 352.8 Ksps, 50/15 uS

# exit

F6


dam1021 uManager Rev 0.99 20150817 FPGA Rev 0.99 Press ? for help.

# filters

04 Bypass FIR1, 352.8 Ksps
08 Linear Phase FIR2, 352.8 Ksps, 0-83 Khz -1 db, 209 Khz -100 db
29 DC Blocking IIR, 352.8 Ksps, 2 Hz HP 1st order
30 Deemphasis IIR, 352.8 Ksps, 50/15 uS

# exit

F7


dam1021 uManager Rev 0.99 20150817 FPGA Rev 0.99 Press ? for help.

# filters

04 Bypass FIR1, 352.8 Ksps
08 Linear Phase FIR2, 352.8 Ksps, 0-83 Khz -1 db, 209 Khz -100 db
29 DC Blocking IIR, 352.8 Ksps, 2 Hz HP 1st order
30 Deemphasis IIR, 352.8 Ksps, 50/15 uS
 
Has anyone seen anything like this before?

If both the SPDIF Toslink and Coaxial interfaces are providing a signal at the same time, while the Coaxial input is used there is an occasional noise/distortion in a periodic pattern. If the Toslink input is selected there are no issues, it happens only on the Coaxial input while there is a Toslink signal present. Disabling the Toslink source makes the issue go away. Its almost as if its taking SPDIF clock from the Toslink interface for Coaxial.

My setup is an X-Fi sound card connected via Toslink (all PC audio except music, resamples everything to 96khz with hardware mixing), Beis AD24QS on Coaxial for vinyl and USB for music with Audacious having exclusive access to the Amanero.

This problem no longer exists in the latest releases, fyi.
 
Yes, the isolated serial port will work just fine with the connection that you mention. I tested it last night.

If you connect both serial ports, whatever you input (or output) to either serial port gets mirrored onto the other one. It is very convenient, especially if you are troubleshooting a microcontroller sending commands to one of the ports. :)