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Reference DAC Module - Discrete R-2R Sign Magnitude 24 bit 384 KHz

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A

acko

Member
Joined 2008
sites.google.com/site/ackodac/home
soekris said:
I don't look that much at the phase noise spec, but instead at the jitter specs. Here the Si514 have max 1 pS RMS, while the best SPDIF receivers have 50 pS RMS, and many people seems to be happy driving a DAC chip directly from a SPDIF Receiver.

The big question is: What can you hear ? I have searched the web and found references to a number of studies, they varied a lot, with hearable limits of 20 pS to 250 nS, with the most credible ones with hearable limits in the nS range.... So I consider 1 pS RMS jitter to be perfectly fine. Especially as once the clock goes though the digital logic it is not 1 pS anymore....
Click to expand...

Specs aside, I one thing that intrigued me is Iancanda's experience with his Si570 clock FIFO, whilst it sounded superbly musical with a sweet spot did not quite match a real live play. When he eventually swapped for a Pulsar Clock the latter sounded closer to the real thing
Maybe there are other opinions but I think there is scope for improvement.
 
andrea_mori

andrea_mori

Banned
Joined 2005
soekris said:
I don't look that much at the phase noise spec, but instead at the jitter specs. Here the Si514 have max 1 pS RMS, while the best SPDIF receivers have 50 pS RMS, and many people seems to be happy driving a DAC chip directly from a SPDIF Receiver.

The big question is: What can you hear ? I have searched the web and found references to a number of studies, they varied a lot, with hearable limits of 20 pS to 250 nS, with the most credible ones with hearable limits in the nS range.... So I consider 1 pS RMS jitter to be perfectly fine. Especially as once the clock goes though the digital logic it is not 1 pS anymore....
Click to expand...

Jitter is the integration of the phase noise, almost the same thing.
1 ps of jitter measured for the Si514 would sound wonderful, but is not real for audio DA conversion.
See post #414, the jitter was measured integrating a bandwidth starting from 12KHz, the Crystek and other oscillators was measured with an integration bandwidth starting from 10Hz or below. There is a reason for that.
 
A

acko

Member
Joined 2008
sites.google.com/site/ackodac/home
Master Mode

soekris said:
....
the DAC can also output a master clock and do have a pin for selecting between 45.1584 and 49.152 Mhz (can be divided).
Same master clock output is also used when connecting multiple DAC's, t.ex. for digital crossovers.
Click to expand...

soekris said:
The DAC design itself is not bound to clock frequencies, but in master mode I'm expecting to support 45/49 from the Si514 ...
Click to expand...

Hi Søren,

Sorry to bombard you with all these questions but I find this Master Mode very interesting:
If setup this way can your DAC then take dual external clock inputs 49.xx/45.xxMhz instead to drive itself? (the on-board Si514 removed or disabled of course)
The CKSEL from your DAC selects the appropriate XOs

Please check and advise
 
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S

Superdad

Member
Joined 2005
acko said:
Specs aside, I one thing that intrigued me is Iancanda's experience with his Si570 clock FIFO, whilst it sounded superbly musical with a sweet spot did not quite match a real live play. When he eventually swapped for a Pulsar Clock the latter sounded closer to the real thing
Maybe there are other opinions but I think there is scope for improvement.
Click to expand...

Well it kind of does not matter, since unless Soren puts a reclocking flop after the FPGA, the jitter from it is likely going to swamp all other efforts. It would be so simple to put a nice flop (maybe Potato chip?) after the FPGA but before the ladders. Maybe make room by moving that long column of bypass caps (one on every FPGA pin?) to the bottom side of the board since they are probably not doing much good so far away anyway.

I'm still looking forward to getting a board to play with. Not sure it will be monotonic beyond about 17 bits--even being sign-magnitude-- but that's okay.
 
G

gentlevoice

Member
Joined 2007
Paid Member
Just a thought ...

Well it kind of does not matter, since unless Soren puts a reclocking flop after the FPGA, the jitter from it is likely going to swamp all other efforts. It would be so simple to put a nice flop (maybe Potato chip?) after the FPGA but before the ladders.
Click to expand...

... and since the board is delayed anyway there might be room/the possibility for implementing a means of a superb clock circuitry - also at the "lowest possible" clock oscillator frequencies (?) - so as to possibly make this DAC unique and - within the reason allowed in future guessing - more future "proof" as it appears to also support higher sampling rates than 384 kHz ...

In case someone would make a PC to I2S/SPDIF "connection" e.g. the HQplayer software to my knowledge allows for 1.536 MHz output at 32 bits ...

Cheers ;-)

Jesper
 
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nautibuoy

nautibuoy

Member
Joined 2010
soekris said:
There is a upper limit of 16.5V, based on capacitor voltage and also to limit loss in linear regulators.

There is a lower limit of 7.5V, based on loss though diode bridge and 5V linear regulators.

Then taking into account line voltage tolerance and transformer no/low load voltage, and we're at 7-8V AC....
Click to expand...

As your board can also accept a DC supply, I'm thinking a 7.4V lipo battery of suitable capacity might be good to try.

I have to say that the discussion points on this topic over the last few days have been really interesting and revealed more of the thinking behind this excellent concept as well as some more possibilities. Thanks.

Ray
 
S

soekris

Member
Joined 2009
soekris.dk
Paid Member
acko said:
Hi Søren,

Sorry to bombard you with all these questions but I find this Master Mode very interesting:
If setup this way can your DAC then take dual external clock inputs 49.xx/45.xxMhz instead to drive itself? (the on-board Si514 removed or disabled of course)
The CKSEL from your DAC selects the appropriate XOs

Please check and advise
Click to expand...

Since the onboard clock, the i2s pins and some gpio pins all goes though the FPGA, there is nothing, except a little more FPGA work and uC coding, to stop me from adding an option of using external clock, much like most regular DAC chips....

The reason why I integrate almost everything is to make this R-2R DAC easier to use and therefore accessible to more people.

Superdad said:
Well it kind of does not matter, since unless Soren puts a reclocking flop after the FPGA, the jitter from it is likely going to swamp all other efforts. It would be so simple to put a nice flop (maybe Potato chip?) after the FPGA but before the ladders. Maybe make room by moving that long column of bypass caps (one on every FPGA pin?) to the bottom side of the board since they are probably not doing much good so far away anyway.

I'm still looking forward to getting a board to play with. Not sure it will be monotonic beyond about 17 bits--even being sign-magnitude-- but that's okay.
Click to expand...

I'm pretty sure that the FPGA itself do not add more jitter than discrete logic chips....

The DAC will not be be monotonic down to more than maybe 14 bits, but thanks to the sign magnitude principle those 14 bits will still be there at the -60 db level, and it will be level linear down to the last bit, way below noise....
 
nautibuoy

nautibuoy

Member
Joined 2010
soekris said:
Since the onboard clock, the i2s pins and some gpio pins all goes though the FPGA, there is nothing, except a little more FPGA work and uC coding, to stop me from adding an option of using external clock, much like most regular DAC chips....

The reason why I integrate almost everything is to make this R-2R DAC easier to use and therefore accessible to more people.
Click to expand...

Søren, does this mean you will make the changes required to facilitate an external master clocks option or that you won't? I can read it either way.

Does having the option to use external clocks preclude your DAC from being easy to use?

Thanks

Ray
 
A

acko

Member
Joined 2008
sites.google.com/site/ackodac/home
soekris said:
Since the onboard clock, the i2s pins and some gpio pins all goes though the FPGA, there is nothing, except a little more FPGA work and uC coding, to stop me from adding an option of using external clock, much like most regular DAC chips....

The reason why I integrate almost everything is to make this R-2R DAC easier to use and therefore accessible to more people.
Click to expand...

Excellent! Thanks for considering this option
Of course, it is good to have the on-board clock as factory default so that users will get a known good system to start with ....
 
G

gentlevoice

Member
Joined 2007
Paid Member
Since the onboard clock, the i2s pins and some gpio pins all goes though the FPGA, there is nothing, except a little more FPGA work and uC coding, to stop me from adding an option of using external clock, much like most regular DAC chips....

The reason why I integrate almost everything is to make this R-2R DAC easier to use and therefore accessible to more people.
Click to expand...

Thumbs up from me as well for considering this - hope it will be possible ;-)

Jesper
 
H

HpW

Member
Joined 2002
hpw-works.com
soekris said:
I'm pretty sure that the FPGA itself do not add more jitter than discrete logic chips...
Click to expand...

Don't be surprised while LSI with various internal switching will add internal power noise and this will generate jitter on the internal level switching... that's why in the old days the output signal has been latched with the master clock.

Additional, do not ignore of the generated HF... it will always follow from the source to a sink... meaning it will follow to the connected systems.

Just my 2 cents

Hp
 
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