Reference DAC Module - Discrete R-2R Sign Magnitude 24 bit 384 KHz

[acko]

Søren, in the context of Potstip's posts, I agree that the SO3 isolator/reclocker is superfluous with the input isolation and reclocking on your DAC board, but, it does have a use in providing external clocking to the Beaglebone so that there is no resampling of incoming data that its single onboard clock would otherwise dictate. With the RPi you're stuck with the resampling anyway.

Now, if the beaglebone could send its clock select flag to your dac and your dac could then switch to the correct clock rate for the data sampling rate and send a suitable clock signal back to the beaglebone.....

Ray

This DAC is fantastic but looks a bit closed with the clocking scheme.
You are spot-on Nautibuoy. If it could take external clock select flag then we can have an end-to-end full synchronous operation!
Also, what are the clock frequencies on the DAC?
Fixed or do they change with Fs?

 

[spzzzzkt]

Multicomp MCFM50/07 yada MCFM70/07 lazimdir. Farnell bunlar satiyor.

Nuvotem Talema also do a number of suitable encapsulated toroidals.

Something like this...
http://uk.rs-online.com/web/p/products/2574941/

or

http://uk.rs-online.com/web/p/toroidal-transformers/2238516/

 

[spzzzzkt]

deleted.

 

[soekris]

Dear Soren

Correct me if i am wrong you design board 7-8v but we can also use 7-15v because all famous troidal transformer manufacturer use 6v then 9v.

So is there any disadvantage use 2 x 9VAC @ 0.83A, can i use this;
15VA Power Transformer

There is a upper limit of 16.5V, based on capacitor voltage and also to limit loss in linear regulators.

There is a lower limit of 7.5V, based on loss though diode bridge and 5V linear regulators.

Then taking into account line voltage tolerance and transformer no/low load voltage, and we're at 7-8V AC....

This DAC is fantastic but looks a bit closed with the clocking scheme.
You are spot-on Nautibuoy. If it could take external clock select flag then we can have an end-to-end full synchronous operation!
Also, what are the clock frequencies on the DAC?
Fixed or do they change with Fs?

If I have to say it myself, the clocking scheme is actually very high performance and flexible.... Have mostly been discussed before but the thread is getting long, so here's a recap:

The DAC have a low jitter digital controlled oscillator (SiLabs si570), data is sent though a FIFO (with programmable lenght) and the FPGA and uC work together to measure incoming bitrate and adjust clock as needed, basically a digital PLL with very fast lock and very slow filtering. So the DAC itself only need serial data, word clock and bit clock, no master clock is needed, it will sync to whatever you feed it.

But the DAC can also output a master clock and do have a pin for selecting between 45.1584 and 49.152 Mhz (can be divided).

Same master clock output is also used when connecting multiple DAC's, t.ex. for digital crossovers.

 

[acko]

If I have to say it myself, the clocking scheme is actually very high performance and flexible.... Have mostly been discussed before but the thread is getting long, so here's a recap:

The DAC have a low jitter digital controlled oscillator (SiLabs si570), data is sent though a FIFO (with programmable lenght) and the FPGA and uC work together to measure incoming bitrate and adjust clock as needed, basically a digital PLL with very fast lock and very slow filtering. So the DAC itself only need serial data, word clock and bit clock, no master clock is needed, it will sync to whatever you feed it.

But the DAC can also output a master clock and do have a pin for selecting between 45.1584 and 49.152 Mhz (can be divided).

Same master clock output is also used when connecting multiple DAC's, t.ex. for digital crossovers.

Excellent!
Thanks for your all your efforts and patience.
I will put my name down for one. Hope it is not too late. Will PM shortly

 

[nautibuoy]

Multicomp MCFM50/07 yada MCFM70/07 lazimdir. Farnell bunlar satiyor.

I suggested the Multicomp a few posts back; perhaps it isn't famous enough.

Ray

 

[soekris]

Just a correction, the digital oscillator used is a Sillicon Labs Si514.

 

[acko]

The DAC have a low jitter digital controlled oscillator (SiLabs Si570) data is sent though a FIFO (with programmable lenght) and the FPGA and uC work together to measure incoming bitrate and adjust clock as needed, basically a digital PLL with very fast lock and very slow filtering. So the DAC itself only need serial data, word clock and bit clock, no master clock is needed, it will sync to whatever you feed

Interesting to see that Si514 (edit) being used but just curious:
What are the actual clock frequencies driving your DAC engine i.e. output of the Si514?
Some posts indicate varying levels up to 100Mhz sweep but you have also indicate dual sync. frequencies 45.xx/49.xx
TIA

 

[TNT]

RS-15-15 Mean Well | Mouser

I know, it's 120mV p-p .... but I already ordered mine

I also have in my possession a DLCP SMPS (50mV):

https://www.hypexshop.com/DetailServlet?detailID=7045

which I will have to test as well...

SMPS spec and SQ don't seem to correlate as one would think...

//

 

[soekris]

Interesting to see that Si514 (edit) being used but just curious:
What are the actual clock frequencies driving your DAC engine i.e. output of the Si514?
Some posts indicate varying levels up to 100Mhz sweep but you have also indicate dual sync. frequencies 45.xx/49.xx
TIA

The DAC design itself is not bound to clock frequencies, but in master mode I'm expecting to support 45/49 from the Si514, that will enable up to 3 Msps. But the Si514 version I'm using can go up to 125 Mhz, so I do have the options to go 90/98 if needed, either for 6 Msps or for higher speed digital filters. But I like to keep clock speed down.

 

[acko]

The DAC design itself is not bound to clock frequencies, but in master mode I'm expecting to support 45/49 from the Si514, that will enable up to 3 Msps. But the Si514 version I'm using can go up to 125 Mhz, so I do have the options to go 90/98 if needed, either for 6 Msps or for higher speed digital filters. But I like to keep clock speed down.

Thanks again!
I reckon 45/49 is good enough for the time being.
Next question, if you do not mind , can your DAC be 'Slaved' to an external clock instead say from a transport clock or external Clock module with CKSEL coming from the external source?

 

[soekris]

Thanks again!
I reckon 45/49 is good enough for the time being.
Next question, if you do not mind , can your DAC be 'Slaved' to an external clock instead say from a transport clock with CKSEL coming from the external source?

I'm not sure what you mean.... The DAC have like a optimized digital PLL, it simply continuously measure the clock, then decide if the internal clock need to be corrected, with the FIFO takes up any slack. And the internal clock is probably better than any external clock over long wires.

So in slave mode it will in principle lock to anything you feed it, don't even need a CKSEL to help. Since you always have a bit clock, either from SPDIF or from I2S, it don't need anything else.

 

[esgigt]

I'm not sure what you mean.... The DAC have like a optimized digital PLL, it simply continuously measure the clock, then decide if the internal clock need to be corrected, with the FIFO takes up any slack. And the internal clock is probably better than any external clock over long wires.

So in slave mode it will in principle lock to anything you feed it, don't even need a CKSEL to help. Since you always have a bit clock, either from SPDIF or from I2S, it don't need anything else.

Søren,

if I understand you correctly, within certain limits the Si514 controlled clock stays constant while the "clock" of the input signal deviates. Could you please explain under which conditions the Si514 controlled clock will change? Or does the answer go too deep, technically speaking? (just trying to understand how it works... )

Thanks in advance,
Edwin

 

[acko]

I'm not sure what you mean.... The DAC have like a optimized digital PLL, it simply continuously measure the clock, then decide if the internal clock need to be corrected, with the FIFO takes up any slack. And the internal clock is probably better than any external clock over long wires.

So in slave mode it will in principle lock to anything you feed it, don't even need a CKSEL to help. Since you always have a bit clock, either from SPDIF or from I2S, it don't need anything else.

Thanks Søren, you have clarified well enough.
I was actually referring to the possibility of an external master clock option to replace the Si514 on your DAC. e.g. using this new Pulsar Clock or similar to improve on the overall jitter performance
I guess the internal operation of your DAC does not allow this mode?
Regardless of clocks, this is an excellent design and the potential to use with external digital filters makes this a standout product. Well done

 

[soekris]

Søren,

if I understand you correctly, within certain limits the Si514 controlled clock stays constant while the "clock" of the input signal deviates. Could you please explain under which conditions the Si514 controlled clock will change? Or does the answer go too deep, technically speaking? (just trying to understand how it works... )

Thanks in advance,
Edwin

It goes something like this:

When not locked, the DAC's FPGA/uC will measure the input clock at very short intervals, until something in a standard sample rate show up.

It will then measure the clock over a little longer time, using that result to program the clock oscillator.

Set FIFO at half full, then open up for audio output.

It will continued to measure input clock over longer time, using that to make small adjustments as needed, the Si514 can be adjusted +-1000 ppm glitchless.

If clock goes out of large range for short period, or smaller range over longer time, the audio will be muted and DAC declared not locked.

FIFO will take up any slack insuring no jitter. If input clock is long term stable then adjustments will be very few and very small.

Repeat.

 

[Tazzz]

From what i can see is in the datasheet the

Si514 is capable off :

100Hz –86dBc/Hz
1 kHz –108dBc/Hz
10 kHz –115dBc/Hz

@156MHz

A common CCHD957 @ 49MHz

100Hz –129dBc/Hz
1 kHz –153dBc/Hz
10 kHz –161dBc/Hz

Assuming the the Phase noise is constant regardless of output frequency should give the Si514 some -9dbc/Hz better numbers at 49Mhz but it still much much noisier.

 

[acko]

It goes something like this:

......

It will then measure the clock over a little longer time, using that result to program the clock oscillator.

...
It will continued to measure input clock over longer time, using that to make small adjustments as needed, the Si514 can be adjusted +-1000 ppm glitchless.

What is the nominal clock frequency?

 

[acko]

Assuming the the Phase noise is constant regardless of output frequency should give the Si514 some -9dbc/Hz better numbers at 49Mhz but it still much much noisier.

Agree, from what I can see the absolute jitter performance depends on the on-board Si514 Clock and will limited by this. Any option to handle a premium external clock will take this DAC to greater heights. From my experience, piping in external clocks over short lengths of coax (50mm) has no detrimental effects. If fact keeping clock generators off the DAC board isolates switching noises from sensitive analog sections

 

[soekris]

From what i can see is in the datasheet the

Si514 is capable off :

100Hz –86dBc/Hz
1 kHz –108dBc/Hz
10 kHz –115dBc/Hz

@156MHz

A common CCHD957 @ 49MHz

100Hz –129dBc/Hz
1 kHz –153dBc/Hz
10 kHz –161dBc/Hz

Assuming the the Phase noise is constant regardless of output frequency should give the Si514 some -9dbc/Hz better numbers at 49Mhz but it still much much noisier.

I don't look that much at the phase noise spec, but instead at the jitter specs. Here the Si514 have max 1 pS RMS, while the best SPDIF receivers have 50 pS RMS, and many people seems to be happy driving a DAC chip directly from a SPDIF Receiver.

The big question is: What can you hear ? I have searched the web and found references to a number of studies, they varied a lot, with hearable limits of 20 pS to 250 nS, with the most credible ones with hearable limits in the nS range.... So I consider 1 pS RMS jitter to be perfectly fine. Especially as once the clock goes though the digital logic it is not 1 pS anymore....

 

[abraxalito]

The big question is: What can you hear ? I have searched the web and found references to a number of studies, they varied a lot, with hearable limits of 20 pS to 250 nS, with the most credible ones with hearable limits in the nS range.... So I consider 1 pS RMS jitter to be perfectly fine. Especially as once the clock goes though the digital logic it is not 1 pS anymore....

What you can hear depends on the DAC chip being used - S-D or multibit. For multibit the jitter tolerance is quite a lot higher - 1pS sounds to me like considerable overkill Those using S-D converters have their work cut out though getting low enough jitter since the OOB HF output folds-down into the audio band as noise when jittered.