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Reference DAC Module - Discrete R-2R Sign Magnitude 24 bit 384 Khz
Reference DAC Module - Discrete R-2R Sign Magnitude 24 bit 384 Khz
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Old 11th February 2019, 07:02 AM   #8701
ynmichael is offline ynmichael
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Join Date: Nov 2015
Don't know if the HC574/HC597 combination that TotalDAC uses has extremely low impedance. It seems to be CMOS technology and the propagation delay is very low ~10ns but nowhere in spec sheet or catalog guides is impedance specified or mentioned. Or is the HC574 used for reclocking?

It seems there might be an unavoidable tradeoff between jitter and ripple in R2R. And I have no idea how bad the jitter in MOSFET can be. But so far it does seem like there's more difference from caps than from clocks. I'll be the first to contribute to a crowdfunded effort for a dam1021 test board and some custom add-on PCB. Maybe we should even ask Soren to sponsor the dam1021.

P.S. The MOSFET datasheet only specifies typical switching characteristic, and it seems pretty precise, down to 0.1ns for single digit figures. Might someone here with more electrical engineering knowledge know whether we should expect the MOSFET to match each other relatively well in switching performance, perhaps dependent on the manufacturing techniques?

Last edited by ynmichael; 11th February 2019 at 07:23 AM.
 
Old 11th February 2019, 07:08 AM   #8702
paulebappie is offline paulebappie  Netherlands
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Location: amsterdam
Quote:
Originally Posted by daniel4381 View Post
Thanks for the suggestion, is it the place where I should put a cap for clock? Can you please give me some more detail, what cap should I use, volt, mfd and orientation.
Quote:
Originally Posted by ynmichael View Post
Why would you want to add a cap, I assume to the clock? There’s really no point. Clock jitter is <1ps, fpga jitter is hundreds of times that.
Source: The Soekris R-2R DAC: Technical Details | H i F i D U I N O

It is a pretty hefty regulator. And it seems the only 3.3v regulator on the board. It must also supply 3.3V to:

3.3V need of the FPGA
Clean side of signal isolators
SPDIF LVDS receivers
Microprocessor
Flash memory
Other components (like the shift registers?)
Good thing it is implemented next to the clock of all places.

Last edited by paulebappie; 11th February 2019 at 07:10 AM.
 
Old 11th February 2019, 07:14 AM   #8703
ynmichael is offline ynmichael
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Join Date: Nov 2015
Doesn't supply shift registers (I think). I don't see why the others matter. Clocking is already very good. Try if you have the cap though seems to be an easy and harmless mod. Do report on ABX results if you have recording equipment... might be a new discovery

Last edited by ynmichael; 11th February 2019 at 07:17 AM.
 
Old 11th February 2019, 07:22 AM   #8704
paulebappie is offline paulebappie  Netherlands
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Join Date: Mar 2006
Location: amsterdam
Datasheet 3v3 regulator: https://nl.mouser.com/datasheet/2/11...117-607727.pdf

"The output of the regulator. A minimum of 4.7F capacitor (0.05Ω ≤ ESR ≤ 0.5Ω) must be connected from this pin to ground to insure stability. For improved ac load response a larger output capacitor is recommended."
 
Old 11th February 2019, 07:24 AM   #8705
ynmichael is offline ynmichael
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Join Date: Nov 2015
I thought Soren said something like a total of 50uF with varying sizes? Idk. Maybe it'll reduce FPGA jitter. Maybe we should try measure before and after... Zfe reported some tiny measurable jitter on stock
 
Old 11th February 2019, 07:54 AM   #8706
ynmichael is offline ynmichael
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Join Date: Nov 2015
Btw on dam1021 we might want to bypass the 5V LDO. TI 78xx lists 17mR as output resistance, I assume the ripples add up over the chain?

See full mod here: Reference DAC Module - Discrete R-2R Sign Magnitude 24 bit 384 Khz

Result looks quite clean. But maybe extra work is needed to save muting circuit? Reference DAC Module - Discrete R-2R Sign Magnitude 24 bit 384 Khz

Last edited by ynmichael; 11th February 2019 at 08:05 AM.
 
Old 11th February 2019, 10:02 AM   #8707
ynmichael is offline ynmichael
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Join Date: Nov 2015
Ideally we could also do reclocking after shift register like totaldac, and only afterwards buffer with MOSFETs. The clock signal can probably be taken from the board directly with careful wiring. Vref caps can also be mounted directly on such an add on board as SMT parts.

I think it’s a worthwhile experiment to take on as a community. There shouldn’t be too much initial costs to cover. But it definitely needs to be a group effort pooling ideas and resources...

I believe the only theoretical question that remains to be answered is whether mosfets are best for “buffering”, and whether they have low enough variances between units in propagation delay time.

Last edited by ynmichael; 11th February 2019 at 10:24 AM.
 
Old 11th February 2019, 06:20 PM   #8708
ynmichael is offline ynmichael
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Join Date: Nov 2015
How to Read a Power MOSFET Datasheet - Jason Sachs

"Sometimes you learn with experience which device parameters have a lot of part-to-part variation, and which ones will tend to tightly cluster around the mean. It’s not something that will be stated in the datasheet; you’ll have to read the manufacturer’s appnotes, contact their applications department, or do your own tests to make those kind of conclusions."

----------

Also found this: www.epboard.com/eproducts/protoadapter.htm
Maybe we can custom order some TSSOP-16 to DIP adaptors?

Last edited by ynmichael; 11th February 2019 at 06:32 PM.
 
Old 11th February 2019, 07:04 PM   #8709
ynmichael is offline ynmichael
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Tolerance Analysis in MOSFET Analog Integrated Circuits | Sylvain Feruglio and Patrick Garda - Academia.edu

If it's within a few percent of 10ns we're probably fine considering there might also be some averaging going on, which could use more mathematical analysis later on. But first someone more familiar with the industry might want to get a more accurate estimate for our particular case...
 
Old 11th February 2019, 07:50 PM   #8710
ynmichael is offline ynmichael
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Join Date: Nov 2015
Btw, the current design also suffers from the possible tolerance mismatch in the shift registers' switching characteristics, even though the shift registers might be balanced within their 8 bits. I'm not even sure if it's better to have "segmented" glitches or some randomness in every bit. Reclocking after shift register might help a bit, provided that the flip-flops are matched more closely, but it's probably similar. In any case, for dam1021 reclocking after shift register might help reduce the jitter from FPGA.

If this experiment bears fruit, which is reasonable to believe based on our current evidence and theories, the ultimate solution that I see is a custom chip that has perhaps 8 or 16-bits for either the purpose of impedance buffering alone, or combined with flip-flop reclocking, whichever has better performance or cheaper if both are equivalent in audible performance. It might offer a small improvement in jitter performance but huge reduction in total PCB area needed, which would make for a great non-DIY product. This would be a much more impressive effort and is probably best taken on by a single individual with the resources, both technical and financial. Perhaps Soren would be interested if the proposed experiment proves to be worthwhile.

Last edited by ynmichael; 11th February 2019 at 08:19 PM.
 

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