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Reference DAC Module - Discrete R-2R Sign Magnitude 24 bit 384 KHz

0.0063%=-84dB=14bitENOB and 0.37%=-49dB=8bitENOB=109dB of D-range
it is surprising performance with 0.05%=11bit resister, especially D-range!

However I doubt it is effective using too much quality resister.
You are using 74LVC595A and NXP's one have on resistance 33Ω at on and 23Ω at off state at Vcc=3V.
How much is the ratio its 10Ω of deviation to ladder resister? about 0.4%?
 
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Jean-Paul, are there any useful techniques to tackle the problem of the "naked" resistors? Using some kind of (plastic) coating?

Normally I use stuff that is designed to dip transformers in. A very slow curing epoxy. I don't know if this would be good for this particular application. It seems like a BB type R2R DAC but then not molded in an epoxy DIL casing thus exposed to the environment.
 
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Impressive! :)
Do you have any linearity, impulse and squarewave plots that you can share with us?

Impulse and square wave plots for a DAC will usefully depict only the digital filter implementation, which Soekris has stated is to be firmware re-configurable within the FPGA. While I would expect a static linearity plot to show some non-monotonic behavior among the lower LSBs, the distortion spectrum plots already provided are a better indicator of A.C. distortion.
 
Impulse and square wave plots for a DAC will usefully depict only the digital filter implementation, which Soekris has stated is to be firmware re-configurable within the FPGA. While I would expect a static linearity plot to show some non-monotonic behavior among the lower LSBs, the distortion spectrum plots already provided are a better indicator of A.C. distortion.

I see, thanks! :)
 
Dear Soekris, could you give some technical details, especially how do you get 28-bit resolution with 0.02% resistors? Is there some kind of software trimming/compensation, perhaps laser trimming? How did you overcome the temperature drift issue (non-zero TK of the resistors)? Resistors below TK=50ppm are quite expensive. What is the source resistance of the swithing elements? How do you provide zero glitch? I am just interested in the theory behind, not the (proprietary) realization. Thanks
 
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First, thanks for the nice words, with an interest like that it will definite move into production, target is 2.5 months from now to availability, there are leadtime on those precision resistors in the quantity needed.... To answer questions are clarify things:

Frequency Response, Impulse Response and Square Wave:

The DAC is bit correct and FAST thanks to the low capacitance compact SMT design. Only limited by the programmable digital filters, a 270 Khz 1st order bessel LPF in output of the R-2R resistor chains and clock speed. A max clock of 100 Mhz will give 6 Msps, although I'm planning to operate at 1.5 or 3 Msps. I will make more measurements, but are limited by equipment available.
Want to do your own filters ? Go to t-filter.appspot.com/fir/index.html, get the filter parameters and wrap them in a header, then download to DAC.
Want no filters ? Just a setting.

Clock:

The board just need data with bitclock, no other input clocks needed. There is a Si514 precision programmable clock generator. The STM32 uC will measure input clock and adjust the Si514 as needed, with data buffered in FIFO, resulting in low jitter bit perfect audio data no matter the input....

Linearity:

As I stated, first measurement was even better than expected, didn't really know upfront what the result would be, but remember that THD is RMS measurements.
A regular DAC feed by the two’s complement code has the problem that zero crossing goes from all zero'es to all ones's, meaning the distortion goes up at lower levels. The sign magnitude DAC architecture basically is two DAC's, one for the positive signal and one for the negative signal, resulting in constant distortion at all levels. T.ex. with a -60 db signal, the 10 most significant bits stays at GND for both the negative and positive DAC sections, not the constant switching of all bits....
It's not something I invented, Burr Brown did it with their Colinear chips, starting with the PCM63.... And my DAC is actually physically two R-2R strings, one with +4V ref and one with -4V reference (of course very low noise and with very precise tracking), connected together at the output which can be done as a R-2R network has constant output impedance.
I also use LVC595 chips as drivers, those have about 13R output impedance at 4V, both positive and negative output fets (I measured some sample parts). I have R as 4K99, 2R is then 10K0 with 3.01M parallel to adjust for driver impedance.

Dust or other environmental issues:

The boards will be manufactured to industrial standards, and due to the low impedance everywhere I don't see any need to go further....

Volume control:

First plan is to just take a std potentiometer and connect to a ADC port on the STM32F030 uC, convert to digital and feed to the FPGA. An encoder is a possibility, GPIO bits are available on a connector, just a question of firmware. Serial port is also available, will be used for control and firmware updates.

Output buffers:

As already said, output drivers can be bypassed, the "raw" R-2R DAC outputs before buffering are available on connector J7, at line level voltage and low impedance. Connect it directly to a power amplifier, a tube buffer, or anything else you prefer.... I like balanced signal so there is an onboard balanced output driver. Later on I might look into doing a version with discrete non NFB output drivers, already have it in my CAD systems....

0.01% version:

Was originally planning for the 0.05% resistor version first, due to leadtime of parts. Will now also put priority to get 0.02% resistor version at the same time. I personally don't see the big need for the 0.01% resistor version, the sign magnitude architecture lower the requirement for resistor precision. But I will look into it, has calculated the 0.01% resistor version to USD 350. And all pricing is for complete and tested board, without connectors mounted so you have flexibility.