Introducing the Buffalo III-SE-Pro 9028/9038

[BrianDonegan]

Originally Posted by francolargo

Problem solved but questions remain. After replacing the I2C isolator on a rig with a 9028, I do indeed have restored access to DAC registers. What confuses me is that I2C only works reliably when a Trident is in place on the VDD_XO during power-up. Apparently, the management chip that holds the reset pin low on startup doesn't successfully activate I2C *without* the XO trident in place. Perhaps a longer 'low-hold' on power up is called-for...

Sounds like the DAC doesn't have a functioning clock in time, I think you are correct to wait longer for the clock to be present.

[alq]

Hello All,
With amanero in slave mode, does VDD_XO need to be omitted and EXT_MCK from Buffalo III SE Pro
connected to U_MCK in Cronus Reclocker (with Rhea modules installed)?

[francolargo]

Originally Posted by BrianDonegan

Sounds like the DAC doesn't have a functioning clock in time, I think you are correct to wait longer for the clock to be present.

Yes, thanks, that was the problem. Instead of using a boot management IC I switched to an isolated GPIO pin, whose timing is easily programmed.

My original design was to be able to use the 100MHz onboard clock with SPDIF, versus an external MCLK with I2S. I'm not succeeding in getting the old 9018s configured via I2C to work with the consumer level SPDIF from the TPA Toslink board. Toslink signal integrity doesn't seem bad (though only 375 mv p-p when connected to the B3, concern?), clock oscillations look good, and I2S is confirmed shut off. Is there still any online info concerning the 9018 register settings from the old B3 stock EPROM?

Many TIA,

Frank

[barrows]

Originally Posted by alq

Hello All,
With amanero in slave mode, does VDD_XO need to be omitted and EXT_MCK from Buffalo III SE Pro
connected to U_MCK in Cronus Reclocker (with Rhea modules installed)?

You can run it two ways:

1. with the Trident in place for VDD XO, and no u.fl cable for the master clock from the Cronus. This uses the ESS chip in asynchronous mode, and resamples all data asynchronously.

2. Without the Trident in place for VDD XO, and with the u.fl cable in place from the Cronus for the masterclock. This runs the ESS chip in the synchronous mode and resamples data synchronously. My opinion is that synchronous mode sounds better, but of course you can try both methods and decide for yourself what you prefer.

[pixelpusher]

Barrows,
Can you use synchronous mode with the standard Twisted Pear firmware?

[barrows]

Yes, I do so all the time. Basically, the DPLL will just "freewheel" as the master clock and bit clock will be synchronous, so the result will be no asynchronous re-sampling. The only drawback is that the ESS chip will no longer "reduce" jitter, but with the Cronus/Amanero this should not be a concern, as this is a very low jitter source.

[alq]

Originally Posted by barrows

You can run it two ways:

1. with the Trident in place for VDD XO, and no u.fl cable for the master clock from the Cronus. This uses the ESS chip in asynchronous mode, and resamples all data asynchronously.
2. Without the Trident in place for VDD XO, and with the u.fl cable in place from the Cronus for the masterclock. This runs the ESS chip in the synchronous mode and resamples data synchronously. My opinion is that synchronous mode sounds better, but of course you can try both methods and decide for yourself what you prefer.

Barrows, thank you. It works in both ways.
The reason why I ask is sporadic static-like noise I have in both modes, sync & async with DSD.
With PCM 352800 Hz in sync mode no sound at all. In async mode there is a lot of noise instead of sound.
All other sample rates are good.
Not sure why... maybe I have to get rid of u.fl cables?

[francolargo]

Originally Posted by francolargo

My original design was to be able to use the 100MHz onboard clock with SPDIF, versus an external MCLK with I2S. I'm not succeeding in getting the old 9018s configured via I2C to work with the consumer level SPDIF from the TPA Toslink board. Toslink signal integrity doesn't seem bad (though only 375 mv p-p when connected to the B3, concern?), clock oscillations look good, and I2S is confirmed shut off.

Just a followup to say that there was no problem with those Toslink outputs. With a bit of background info from Brian I got everything sorted out. Again, performance of the es9018+Mercury I/V is quite pleasing (we're building with 9018s, a 9028, and a 9038 for family). Also pleasing is the casework done mostly by my son... Aluminum bases & back, 1/4" brass fronts and DIY knobs, granite/acrylic laminated sides, acrylic tops laser-cut for ventilation.

Full disclosure: "Largo" is a family joke meaning "from the minds of imposters". But with "Twisted Pear Inside", the imposters are covered...

[barrows]

Originally Posted by alq

Barrows, thank you. It works in both ways.
The reason why I ask is sporadic static-like noise I have in both modes, sync & async with DSD.
With PCM 352800 Hz in sync mode no sound at all. In async mode there is a lot of noise instead of sound.
All other sample rates are good.
Not sure why... maybe I have to get rid of u.fl cables?

I have no such problems, using u.fl cables at 10 cm or less. 352.8 may require a higher clock speed? It has been awhile before I have tested that. Mine works perfectly for DSD up to DSD 256 with a 45.1584 clock on the Cronus, DSD 512 would require a 90.3168 clock. I will test with PCM 352.8 and let you know for sure (DSD input sounds so much better to me I oversample everything to DSD 256 for playback). I am using amanero firmware 2006be 11 and CPLD 1081 slave for best performance with DSD (will work for native DSD on linux in my case).

[alq]

Originally Posted by barrows

I have no such problems

Thank you!
It seems like an amanero module has a problem. I have tried different firmware with same result.