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Cronus - It's about time.

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Joined 2003
Paid Member
<SNIP>

If so, mount a single 22.5792 clock (I prefer NDK SDA series with .01 uF bypass on the Rhea board) to have the lowest phase noise (unless you have a Pulsar clock around) and set the clock divider at 1:1 for Amanero.

<SNIP>

Barrows, NDK SDA over Crystek CCHD-957?

That's been my recent preference too, but that's not a universal recommendation.

Just checking!

TIA!

Greg in Mississippi
 
Hi Greg,

Yes, Gordon measures them (he has an analyzer which can measure phase noise down to 2 Hz!) and he said the NDK SDA series consistently outperform the Crystek 575 and 957 series parts. The fact that he has measured a lot of them is important, because these oscillators vary a bit from part to part. I am sure some folks might "prefer" the "sound" of Crystek, but they are less accurate as per Gordon's phase noise measurements. I posted this here because this is not an "impression" (although it has been my impression for sonics) but because is measured performance which is not questionable.
At Sonore we have some very good test instruments, and can measure DAC jitter very accurately, we do not have the instrument necessary to measure XO phase noise directly so precisely-Gordon does.

Luca: Yeah, I think 0805 works, I hand soldered them with a magnifier, and I am really no good with parts much smaller than that! The NDK clocks can be a challenge, be careful not to overheat them.
 
Amanero

@ barrows, what settings firmware do you use for Amanero?

Last news I have from Amanero:

CPLD
Slave_1081_DSDSWAPPED

CPU
firmware_2006be10

Have I to change the Configuration bits or something else more?

TIA
Felipe

I have a couple. One is running the older firmware, I think it is 1099rc?, this is in my BuffaloPro DAC, so it is running CPLD 1081 slave. This firmware works perfectly for DSD 256 (on Limux from a Sonore Renderer), and that is how I run it on the BuffaloPro, with either Roon or HQPlayer oversampling everything to DSD 256.
On the new Amanero, I asked Brian (from TPA) to flash it with the newer 2006be10 which is supposed to work well up to DSD 512, also with CPLD 1081 slave. I do not have a Windows machine here, except when my GF is around, so I can only re-flash myself occasionally. I do not remember the whole flashing process since last time I did it, but if you Google it there are instructions around on the net.
This second one with Cronus is going to be paired with my DSC-2 build, and hopefully I'll get a new server built up which can run HQP with the new EC modulators at DSD 256 (there are no processors which can run the EC modulators at DSD 512, Jussi says, probably an 8 GHz processor would be required!).
 
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Joined 2009
Paid Member
Ah, I understand. Attached images if someone else can help, I will also ask Domenico from Amanero. I you want I flash for you but I'm living in Europe so I guess anybody near you can help you better and faster.
 

Attachments

  • Config bits 17-10-2019.png
    Config bits 17-10-2019.png
    34.8 KB · Views: 219
  • latest firmware + reclock 17-10-2019.png
    latest firmware + reclock 17-10-2019.png
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Felipe, if you Google for information on firmware flashing for Amanero you will find some instructions. Thanks for the offer, my GF is around with her Windows machine often enough that I can change the firmware if I need to, it has just been awhile since I did it last. But I do not recall needing to change the settings much, if at all, just the main firmware and the CPLD for slave, or not. I do not worry about DSD swapped or not, as I only send DSD, so I can swap the u.fl to make sure channel mapping is correct.
 
As I recall mine are set as in the picture, and I appear to have no issues with both 1099rc and 2006be, both with slave 1081 for use with the Cronus.
For the DSC-2 I will be using an adapter (with isolation) which allows me to get the mute signal directly from the Amanero board (isolated on the adapter) so I do not have to reconfigure anything to get mute through the Cronus' output.
The BuffaloPro does not need Mute, as the DAC itself is seems to be well behaved in this regard. But, i am always sending only DSD 256, so I do not have to worry about problems caused by sample rate switching.
 
"The bit clock pulses once for each discrete bit of data on the data lines. The bit clock frequency is the product of the sample rate, the number of bits per channel and the number of channels."

I might understand in the end. Digital is an unknown land of mine...
Thank you, miero