I'd lay money on this being in development, but I also imagine it's going to be a long development!
This post and many of the others above are getting off-topic so I expect Brian will be clearing them out soon.
Maybe a thread should be started along the lines of: "In Development".
I am working on it right now.
I am implementing an XMOS based solution. Stay tuned.
I am guessing first prototypes are 6-8 weeks off. Just depends on other time demands.
Cheers!
Russ
I am working on it right now.
I am implementing an XMOS based solution. Stay tuned.
I am guessing first prototypes are 6-8 weeks off. Just depends on other time demands.
Cheers!
Russ
Russ,
What is the jitter on a clock divide (I suppose you divide the incoming clock to get the bit clock for the I2S). On FPGAs the jitter is specified ~150 psec added for clock division, but I couldn't find the jitter spec for the XMOS device... thanks..
You don't have to clock divide at all if you really don't want to. One could reclock all data to the highest supported rate. In any case it is not something I am going to worry about much. Any device that produces one clock based on another is going to introduce some phase noise. I think the FPGA number you quote is likely dependent on he device and the technique used. The XMOS device is very definitely not an FPGA.
There is documentation from XMOS on I/O timing. A little poking around and you will find it.
I have been using the XMOS for a while now with some custom firmware and I am quite happy with it.
The module I have right now currently supports up to 352.8khz 32bit and the one I am currently designing will support sample rates up to 384khz 32bit. Currently I2S output is only being considered, but I will likely support SPDIF output as well but will probably need to limit that to 192khz 24bit since most receivers cannot go beyond this.
I am aiming to make it support up to 8 channels of I2S output (yes even at 384khz). I have not decided that part yet.
One could reclock all data to the highest supported rate. In any case it is not something I am going to worry about much. Any device that produces one clock based on another is going to introduce some phase noise. I think the FPGA number you quote is likely dependent on he device and the technique used. The XMOS device is very definitely not an FPGA. There is documentation from XMOS on I/O timing. A little poking around and you will find it.
I have been using the XMOS for a while now with some custom firmware and I am quite happy with it.
The module I have right now currently supports up to 352.8khz 32bit and the one I am currently designing will support sample rates up to 384khz 32bit. Currently I2S output is only being considered, but I will likely support SPDIF output as well but will probably need to limit that to 192khz 24bit since most receivers cannot go beyond this.
I am aiming to make it support up to 8 channels of I2S output (yes even at 384khz). I have not decided that part yet.
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It's quite marvelous! A great innovation!
What kind of modules do you have? XS1-G Development kit?
Do you mean the current or new USB(2.0) audio or ASIO driver software on PC sides(Windows/Mac OS/Linux) supports this sampling rate as well?
Hi Bunpei,
I am using the XMOS USB 2.0 audio module with custom firmware and some slight hardware mods right now, and designing my own solution in the mean time. I also have their driver along with some work of my own.
Drivers will be somewhat a challenge, at least in regard to Windows. I am working that out as well. For now I am having to rely and what I can either write myself or get from XMOS.
The important thing is that the hardware hurdle is solved. The driver hurdle is completely solvable as well.
More details as I can give them. Things are progressing.
Cheers!
Russ
I am using the XMOS USB 2.0 audio module with custom firmware and some slight hardware mods right now, and designing my own solution in the mean time. I also have their driver along with some work of my own.
Drivers will be somewhat a challenge, at least in regard to Windows. I am working that out as well. For now I am having to rely and what I can either write myself or get from XMOS.
The important thing is that the hardware hurdle is solved. The driver hurdle is completely solvable as well.
More details as I can give them. Things are progressing.
Cheers!
Russ
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Drivers will be somewhat a challenge, at least in regard to Windows. I am working that out as well. For now I am having to rely and what I can either write myself or get from XMOS.
The important thing is that the hardware hurdle is solved. The driver hurdle is completely solvable as well.
I appreciated your explanation very much! Thank you.
May I understand that you have already succeeded in playing a whole DXD file in your preliminary environment that cosists of PC or Mac, USB 2.0 I/F and modified XMOS USB audio 2.0 reference board?
Bunpei
Indeed I have.
Right now the Mac is the simplest route.
And if I were not under NDA I would explain exactly how I am doing it.
Cheers!
Russ
Indeed I have.
Right now the Mac is the simplest route.
What an admirable achievement!
It will much facilitate a spread of DXD file play in audiophile communities.
I believe DXD files are worth listening and hope more sources available other than those in 2L leading-edge demonstration.
Bunpei
You don't have to clock divide at all if you really don't want to.
...
I don't worry about that either. Just some theoretical/engineering sanity check to balance all the "ear-only" engineering out there
Thanks for the update.
Anyone have a wiring diagram?
Hi,
I'm taking on a BuffaloII as my first DIY project and so far I'm having great fun. I've assembled the DAC, IVYIII, Placid and Placid BP. I'm planning on building it to be fed with both a toslink module and a USB/SPDIF converter and installing both single-ended and balanced outputs. I might be able to figure it out, but I'm not sure and would rather be safe than sorry. Can anyone help?
Cheers
Will
Hi,
I'm taking on a BuffaloII as my first DIY project and so far I'm having great fun. I've assembled the DAC, IVYIII, Placid and Placid BP. I'm planning on building it to be fed with both a toslink module and a USB/SPDIF converter and installing both single-ended and balanced outputs. I might be able to figure it out, but I'm not sure and would rather be safe than sorry. Can anyone help?
Cheers
Will
You don't have to clock divide at all if you really don't want to.
I suppose if you send 44.1K material at 8X re-sampled, this would correspond to 352.8K (which you plan to support). With 32bit per channel I2S, this corresponds to a clock of 22.5792 MHz. Makes sense, makes sense...
Are you planning and I2C interface for the board? Also since the chip is basically a computer, would you add HDCD with transient filters?
Dear Russ:
outstanding work!
You have a customer in me for a few of them I might be old fashioned using only Windows XP SP3 on my computers
May I ask what chip you have signed an NDA for?
Regards,
outstanding work!
You have a customer in me for a few of them
I might be old fashioned using only Windows XP SP3 on my computers May I ask what chip you have signed an NDA for?
Regards,
Indeed I have.
Right now the Mac is the simplest route.
And if I were not under NDA I would explain exactly how I am doing it.
Cheers!
Russ
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