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Jan's HV regulator
Jan's HV regulator
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Old 20th October 2019, 06:12 PM   #41
Elvee is offline Elvee  Belgium
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Quote:
.....
More to the point, I see a few potential problems:

From an AC perspective, the opamp operates in unity-gain, with 100% feedback, and to ensure stability the feedback path must introduce a minimal phase-shift between the opamp output and its - input, and this has to be true between 0 and ~80MHz, since no local compensation is present.

The gate stopper and the MOS capacitances create a first pole, meaning any other pole along the path will lead to instability.
Such a pole could be created by the protection resistors and a capacitive load for instance.
A quick, simplified sim shows that the regulator is marginally stable on a resistive load and becomes unstable with a capacitor of a few nF.
The reality could be somewhat different, but very much will depend on the exact load, the way it is wired, etc, and this is not controllable on the board itself, meaning it should be reasonably immune to impedance effects.
The + input connection also contributes to complicate the problem.
For these reasons, I think that a minimum of local compensation should be included.

Other problems could be caused by C4: it will be charged to the output voltage, and in case of a short, it will discharge through D3.
The energy will be low, but after some events a small diode like the 1N4148 might well fail.
Note that the "short" does not need to be a hard, physical one: the connection to a completely discharged bypass cap will have the same effect.
Less obvious is the case of load-dumping: there is apparently no good reason for such an event to occur, but in practice HV circuits can sometimes see this kind of situation, especially in an experimental/DIY setup.
If the output voltage increases brutally over the normal, set voltage (a cap discharge, short to another supply...) the whole regulator including the opamp will rise higher than C4, leaving the + input protected only by the 100 ohm series resistor.

For these reasons, it would be preferable to place two anti parallel diodes directly across the inputs, possibly schottky types.

In case of an output short, another component will be stressed: R10.
It will have to withstand a high surge current, and should be a pulse-resilient type.

Something optional, but cheap and contributing to the overall reliability would be the inclusion of a series resistor (preferably fusible-type) in the drain of Q8: up to 1K will have no impact on the performance and could save the day in case the MOS encounters the occasional rogue pulse
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Old 20th October 2019, 06:18 PM   #42
obseedian is offline obseedian  Canada
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Pretty sure C6 and R10 is the compensation. (but may need to increase C6 and/or reduce R10 for improved stability)

Last edited by obseedian; 20th October 2019 at 06:21 PM. Reason: Change typo C4 to C6
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Old 20th October 2019, 06:30 PM   #43
jan.didden is offline jan.didden  Europe
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Yes, C6 and R10 have been dimensioned to maintain stability even with zero capacitance downstream.

Jan
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Old 21st October 2019, 09:27 AM   #44
Elvee is offline Elvee  Belgium
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I am convinced that the regulator in itself is stable and doesn't need additional bypass, but it goes further than that: it might not tolerate a bypass cap directly connected across the output terminals.

The issue is common to high gain, high feedback amplifiers: for example, if you connect a 100nF capacitor directly to the output of an audio amplifier, upstream of the inductive zobel it will most of the times cause oscillations.

Voltage regulators are a particular class of amplifiers having a single-quadrant output, but they are subjected to the same general rules.
They are normally compensated in a way that makes them tolerant to capacitive loads, because that is the way they are normally used. Even then, a minimal esr value is sometimes required to ensure stability.
R6 is a very explicit series resistor, and it adds a zero in the response, but an additional, pure cap might cancel the stabilizing effect of this zero.

I have no idea about the way the circuit is going to behave in reality, because so many factors play a role, but having such a large R10 is like a door open to the outside world: internal loop stability issues will be influenced by the nature of the external load.
With a "hard" decoupling capacitor, the door is completely closed for high frequencies, and the regulator becomes just a black box delivering voltage and current, without further interaction.

Testing the response with current steps, together with various reactive loads could provide valuable information about the loop stability
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Old 22nd October 2019, 06:30 PM   #45
Elvee is offline Elvee  Belgium
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Improving the stability can be as simple as opting for a more placid, some would say sensible opamp.


Here is the simplified loop gain sim (the exact details will certainly differ in reality, but it gives a broad idea of what to expect).
With a 47nF cap, the phase margin is -23°, meaning it will be unstable:

Jan's HV regulator-jan1-png

If the opamp is changed for a LT1677 (GBW=7.2MHz), the circuit becomes marginally stable, with a 8° margin.
Note that the performances have not been degraded, in fact the opposite is true: the 100Hz loop gain (dictating the ripple rejection) has improved by ~15dB:

Jan's HV regulator-jan2-png

With a small cap across the gate-stopper, this margin is almost doubled:

Jan's HV regulator-jan3-png
Attached Images
File Type: png Jan1.png (109.1 KB, 207 views)
File Type: png Jan2.png (95.3 KB, 204 views)
File Type: png Jan3.png (95.7 KB, 203 views)
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Old 23rd October 2019, 12:41 AM   #46
obseedian is offline obseedian  Canada
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Elvee I don't think your loop gain probe placement is correct. AD8031 has only about 80dB of open loop gain, should not be getting over 160 dB of loop gain. In any case lowering R3 and increasing C1 improves phase and gain margin.

Jan's HV regulator-probe-png
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Old 23rd October 2019, 06:13 PM   #47
Elvee is offline Elvee  Belgium
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I think you are right: I probed it that way because the regulator is referenced to the output, meaning the gain of the MOS operating in common-source has to be taken into account, except that here the configuration is hybrid.

Although the regulator circuit is referenced to the output, the reference voltage is in fact tied to the ground, meaning it acts as a follower.

To take the whole situation into account, including common mode effects of the opamp, it is probably necessary to probe it that way:

Jan's HV regulator-jan4-png

Ideally, a more sophisticated probe would be necessary to include the loading effect on the output, but here with the simplifications it is probably sufficient, and including the opamp supply in the probe changes practically nothing, thanks probably to its good common-mode rejection.

The LF gain is substantially reduced, but the HF behavior remains essentially similar, and the negative phase margin is still present, it is even a bit larger.

The same remedies apply, and have a similar effect, and if they are combined to your fixes, it is probably possible to arrive at a satisfactory solution, but it has to be tested in practice, because tailoring the compensation around a 47nF load will certainly be non-ideal for all other values (it is an example I took randomly).

Jan's HV regulator-jan5-png
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File Type: png Jan5.png (93.1 KB, 140 views)
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Old 23rd October 2019, 06:59 PM   #48
jan.didden is offline jan.didden  Europe
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The regulator has been designed to be stable without external output capacitance. Adding output capacitance makes it more stable.

Jan
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Old 23rd October 2019, 07:05 PM   #49
jan.didden is offline jan.didden  Europe
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Quote:
Originally Posted by obseedian View Post
In any case lowering R3 and increasing C1 improves phase and gain margin.
The value of 1uF for C1 was a practical value as to size/voltage limit (630V) on the PCB. Design target was 600V input and thus possibly 600V output.
With that part in mind, R3 was selected for best stability in several prototypes.

I did look at larger caps at 630V, but to my surprise 600V+ electrolytics are very rare.

Jan
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Old 23rd October 2019, 10:02 PM   #50
Elvee is offline Elvee  Belgium
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Quote:
Originally Posted by jan.didden View Post
The regulator has been designed to be stable without external output capacitance.
That is clearly the case
Quote:
Adding output capacitance makes it more stable.
Facts cannot be refuted, thus reality has to be the ultimate test: there are many effects and parasitics involved, and a simplified sim cannot replicate the fine details.

The topology of a buffer based on a fast, high gain uncompensated amplifier rang an alarm bell for me, because when combined with a capacitive load, it is generally a recipe for instabilities, and the sim seemed to confirm this analyzis, but the specifics matter, and if it is stable all is fine.


In general, instabilities will occur for a particular range of capacitances: too small, and they are beyond the unity gain limit, too large and the ratio of esr to reactance becomes larger for physical and mathematical reasons, damping possible instabilities.

Note that the output is not necessarily the best spot to detect some types of oscillations: if they are in the VHF range, the capacitor that causes them is going to attenuate them to the point of making them invisible with an oscilloscope and a regular X10 probe.
The output of the opamp would make a better test point.

Anyway, a step-test is always a valuable and revealing tool.




Quote:
Originally Posted by jan.didden View Post
I did look at larger caps at 630V, but to my surprise 600V+ electrolytics are very rare.
It is a technological limit, linked to the properties of aluminum oxide.
The alternative, tantalum, has an even lower limit, so unless another miracle element is found, the 550V~600V limit is here to stay
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