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Old 20th September 2021, 02:20 AM   #3101
Koonw is offline Koonw
diyAudio Member
 
Join Date: Apr 2013
Type 50 RCA model:


Code:
**** 50 ** Advanced Grid Current **********************************
* Created on 09/20/2021 10:04 using paint_kit.jar 3.1
* Model Paint Tools: Trace Tube Parameters over Plate Curves, Interactively
* Plate Curves image file: 50.png
* Data source link: 
*----------------------------------------------------------------------------------
.SUBCKT 50 1 2 3 ; Plate Grid Cathode
+ PARAMS: CCG=4.2P  CGP=7.1P CCP=3.4P 
+ MU=3.832 KG1=4456.66 KP=38.05 KVB=3355.76 VCT=-0.18 EX=1.324 
+ VGOFF=-0.6 IGA=0.001 IGB=0.3 IGC=8 IGEX=1.64 
* Vp_MAX=800 Ip_MAX=120 Vg_step=20 Vg_start=0 Vg_count=9
* Rp=4000 Vg_ac=55 P_max=40 Vg_qui=-48 Vp_qui=300
* X_MIN=10 Y_MIN=40 X_SIZE=830 Y_SIZE=619 FSZ_X=1296 FSZ_Y=736 XYGrid=true
* showLoadLine=n showIp=y isDHT=n isPP=n isAsymPP=n showDissipLimit=y 
* showIg1=y gridLevel2=y isInputSnapped=n  
* XYProjections=n harmonicPlot=n dissipPlot=n 
*----------------------------------------------------------------------------------
E1 7 0 VALUE={V(1,3)/KP*LOG(1+EXP(KP*(1/MU+(VCT+V(2,3))/SQRT(KVB+V(1,3)*V(1,3)))))} 
RE1 7 0 1G  ; TO AVOID FLOATING NODES
G1 1 3 VALUE={(PWR(V(7),EX)+PWRS(V(7),EX))/KG1} 
RCP 1 3 1G   ; TO AVOID FLOATING NODES
C1 2 3 {CCG} ; CATHODE-GRID 
C2 2 1 {CGP} ; GRID=PLATE 
C3 1 3 {CCP} ; CATHODE-PLATE 
RE2 2 0 1G 
EGC 8 0 VALUE={V(2,3)-VGOFF} ; POSITIVE GRID THRESHOLD
GG 2 3 VALUE={(IGA+IGB/(IGC+V(1,3)))*(MU/KG1)*(PWR(V(8),IGEX)+PWRS(V(8),IGEX))}
.ENDS 
*$

DHT model:


Code:
**** 50 ** Composite DHT with Advanced Grid Current **************
* Created on 09/20/2021 10:06 using paint_kit.jar 3.1
* Model Paint Tools: Trace Tube Parameters over Plate Curves, Interactively
* Plate Curves image file: 50.png
* Data source link: 
*----------------------------------------------------------------------------------
.SUBCKT DHT_50_A2 1 2 3 4 ; P G K1 K2
+ PARAMS: CCG=4.2P  CGP=7.1P CCP=3.4P RFIL=6
+ MU=3.832 KG1=4456.66 KP=38.05 KVB=3355.76 VCT=-0.18 EX=1.324 
+ VGOFF=-0.6 IGA=0.001 IGB=0.3 IGC=8 IGEX=1.64 
* Vp_MAX=800 Ip_MAX=120 Vg_step=20 Vg_start=0 Vg_count=9
* Rp=4000 Vg_ac=55 P_max=40 Vg_qui=-48 Vp_qui=300
* X_MIN=10 Y_MIN=40 X_SIZE=830 Y_SIZE=619 FSZ_X=1296 FSZ_Y=736 XYGrid=true
* showLoadLine=n showIp=y isDHT=y isPP=n isAsymPP=n showDissipLimit=y 
* showIg1=y gridLevel2=y isInputSnapped=n 
* XYProjections=n harmonicPlot=n dissipPlot=n 
*----------------------------------------------------------------------------------
RFIL_LEFT    3  31 {RFIL/4}
RFIL_RIGHT   4  41 {RFIL/4}
RFIL_MIDDLE1 31 34 {RFIL/4}
RFIL_MIDDLE2 34 41 {RFIL/4}
E11 32 0  VALUE={V(1,31)/KP*LOG(1+EXP(KP*(1/MU+V(2,31)/SQRT(KVB+V(1,31)*V(1,31)))))}
E12 42 0  VALUE={V(1,41)/KP*LOG(1+EXP(KP*(1/MU+V(2,41)/SQRT(KVB+V(1,41)*V(1,41)))))}
RE11 34 0 1G
G11 1 31 VALUE={(PWR(V(32),EX)+PWRS(V(32),EX))/(2*KG1)}
G12 1 41 VALUE={(PWR(V(42),EX)+PWRS(V(42),EX))/(2*KG1)}
RCP1 1 34 1G
C1 2 34 {CCG} ; CATHODE-GRID
C2 2 1 {CGP} ; GRID=PLATE
C3 1 34 {CCP} ; CATHODE-PLATE
RE2 2 0 1G
EGC1 81 0 VALUE={V(2,31)-VGOFF} ; POSITIVE GRID THRESHOLD
GG1 2 31 VALUE={0.5*(IGA+IGB/(IGC+V(1,31)))*(MU/KG1)*(PWR(V(81),IGEX)+PWRS(V(81),IGEX))}
EGC2 82 0 VALUE={V(2,41)-VGOFF} ; POSITIVE GRID THRESHOLD
GG2 2 41 VALUE={0.5*(IGA+IGB/(IGC+V(1,41)))*(MU/KG1)*(PWR(V(82),IGEX)+PWRS(V(82),IGEX))}
.ENDS 
*$
Attached Images
File Type: jpg 50 RCA paint.jpg (467.1 KB, 195 views)
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Old 28th September 2021, 05:10 AM   #3102
Koonw is offline Koonw
diyAudio Member
 
Join Date: Apr 2013
Default Export and Import Netlist

LTSpice exports netlist to about 20 external layout softwares. Here I share with you the ways. The netlist pin order exported from LTspice is based on the model pins (1, 2, 3,..) order, the pins number must be reassigned in the actual layout footprint as shown. You can add more pins like heaters to the tube model and asy symbol, and they will still be running so long both the model pin and asy pin order are same. You split the original into two half sections, be it twin triode or pentode triode, and make separate footprint for each section and regroup to form group footprint so they're not shift in anyway. Do not change the net order of pin or model. Use text to label the asy model/actual pins so make it easy to reassign later.
Attached Images
File Type: png LTSpice netlist export-1.png (50.8 KB, 150 views)
File Type: png LTSpice netlist Express PCB import.png (123.9 KB, 146 views)
File Type: png net.png (14.7 KB, 149 views)
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Old 28th September 2021, 09:43 AM   #3103
Adrian Immler is offline Adrian Immler  Switzerland
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Join Date: Oct 2018
Location: East Border of Switzerland
Cool stuff, Koonw!
That may safe a lot of drawing time when one intend to build a PCB for a tube amp. 👍
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Old 30th September 2021, 12:43 PM   #3104
gerrittube is offline gerrittube  Netherlands
diyAudio Member
 
Join Date: Jan 2018
Location: Holten
Default LTSpice phase splitter not working

I'm quite new to LTSpice and have only made a few simulations so far. I have drawn a diagram of my (working) driver stage. For some reason the phase inverter doesn't invert in LTSpice. In reality it does...

How do I get a proper simulation of the phase splitter?

Note: the 10M90S in this diagram will be used later on, this code is not needed right now.

Regards, Gerrit
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Old 30th September 2021, 01:11 PM   #3105
Koonw is offline Koonw
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Join Date: Apr 2013
Just change 1m to 1Meg, if you mean R5 is 1 Mega ohms.
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Old 30th September 2021, 02:40 PM   #3106
gerrittube is offline gerrittube  Netherlands
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Join Date: Jan 2018
Location: Holten
Hi Koonw,

This was indeed my problem. With 1Meg it works fine!

Regards, Gerrit
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Old 4th October 2021, 01:21 PM   #3107
gerrittube is offline gerrittube  Netherlands
diyAudio Member
 
Join Date: Jan 2018
Location: Holten
Hi,

Is there something like LTSpice for an iPad? I couldn’t find it.
I would like to be able to at least open .asc files with my iPad.

Regards, Gerrit
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