But looking from the point of view of quiescent bias current for the MOSFET, you need to account for ther 'load current' throuhgh Cds, right?
So, if I want to calculate the quiescent current (class A) that I need to swing the load cap through the full voltage range, I have to calculate for Cload + Cds + Cdg, right?
Jan
The current charging Cds subtracts from the drain current and Cds ends up getting charged by some of the pullup current (to the first order). I thought this was intended as an open loop circuit? I either case the DC bias needs to be enough to supply the max displacement current in Cds to remain well behaved.
That's what I thought. Interesting case when the load capacitance is largely caused by the intrinsic Cds and Cgs. I was thinking, well I just put two in parallel but obviously that has a very small advantage only in such cases, not worth the effort.
And it will be closed loop.
Jan
some depends on the cascode series gate resistor R11 value..... compare with zero Ohms and 1 meg. The degree of effect of the Cdg and Cgs and that R11 ---- assuming gate bias source Z is zero.
THx-RNMarsh
Last edited:
I would like to stay corrected: Crown also
Crown Audio files notice of first half of layoffs Only four years ago: Crown Audio announced plans to expand its operations that will lead to 44 new jobs in Elkhart
I would like to stay corrected: Crown also
Only four years ago: Crown Audio announced plans to expand its operations that will lead to 44 new jobs in Elkhart
It seems from experience that plans like expanding all go out the window when the parent company gets bought out. Especially affected are any duplications.
-RNM
OK, got further and accomodated the Cds & Cdg current. Circuit runs on the sim as expected.
But (there always is a but) I assume that that displacement current does not cause dissipation in the device. Is that correct? To calculate the dissipation I should account for the total device current but subtract the part that is due to the 'shunting' parasitic capacitance current to get at the current that needs to be multiplied by the device voltage (RMS fashion) to determine the dissipation. Yes?
Jan
Jan, do you use Spice (LTspice) simulator. It should do all that if models are correct.
Damir
Not necessarily, you want the true power in the FET which will depend on the phase angle of the net current and voltage. As Damir said this should be built into any simulator, it's fundamental.
Power in AC circuits
Power in AC circuits
Damir & Scott, beg to differ. Yes, LTspice gives me dissipation in any color I want, but the way I see this is as follows.
The current LTspice 'measures' is based on the mesh current flowing (in the case of my MOSFET) from D to S. But intrinsically to the device are the capacitances like Cds. So if I ask LTspice to .measure the dissipation as the product of device current and device voltage (RMS fashion) the Cds current is included, although it does not (I believe) contribute to heating.
Edit: do you mean that the phase shift of the device current to the device voltage, as result of Cds, is automagically taking care of this through the complex calculation?
Jan
The current LTspice 'measures' is based on the mesh current flowing (in the case of my MOSFET) from D to S. But intrinsically to the device are the capacitances like Cds. So if I ask LTspice to .measure the dissipation as the product of device current and device voltage (RMS fashion) the Cds current is included, although it does not (I believe) contribute to heating.
Edit: do you mean that the phase shift of the device current to the device voltage, as result of Cds, is automagically taking care of this through the complex calculation?
Jan
Last edited:
Kirchoff's law says that Id will remain constant at DC no matter what, and I assume output voltage will be constant at DC as well. That leaves a few parasitic mechanisms I can see. The portion of Icds that diverts through Csg will cause dissipation in Rg. The current through Cdg will also cause dissipation in Rg. Fast signals may cause parasitic dissipation in as much as the MOSFET gate begins to work like a detector and shift the bias point.
This confusion disappears completely when you replace the MOSFET by its small signal equivalent circuit (Cgs, Cgd, Cds, gm, gds). Now you can measure each individual current and each individual power dissipation, independently. No more worries about how the "LTSPICE mosfet model" currents are opaquely commingled.
Sure, but the point is that in LTspice the MOSFET with its capacitances are part of the model black box, and the currents can not be seperated apart if you define P as Id * Vds.
In jcx's example, if you alt-clk the C in my rudimentary circuit it tells you the dissipation is 320mW versus 100mW in the R. But of course the dissipation in the C, as in 'making heat', is pretty much zero.
And the reason is that LTspice doesn't really calculate power, it calculates I * V.
So in my case where the actual current through the MOSFET parasitics is about equal to the 'real' device current (the one that gives rise to heat), the dissipation figure is twice as what it really is. Saves a lot on the heatsink.
Edit: I just went back to my circuit and changed the C-values in the model of the Vas device, and the power from the .meas does change a little; I really don't know how the caps in the model interact but there is a change.
Jan
Last edited:
- Status
- Not open for further replies.