Is this a good design?

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Hi, this is my first post, so be nice :)

I am designing a driver for a passive LCR style equalizer.
It is going to be in a bass preamp/eq, so I am designing for as high headroom as I can.



The Goals:

The amp has to drive around a 1k impedance or so without clipping.

so I aim to be able most of the supply rails into the load.

Also I aim to stay *just about* in class A throughout. (Because no global feedback)



The circuit seems to simulate well, however this is my first attempt at such a driver (I usually design with tubes)

Is this a good design for my needs? Will the bias be stable, etc?


Thanks in advance!
 

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WELCOME

This should work, with high input impedance and low output impedance probably below 10ohm and not very high distortion.

However :
-why so high supply valtage? a bit high for these jfets, also does it buffer signal from active bass pickups? It will be probably below 1V ac

-cascade of three followers is not nessesary for low powers, jfet driving complementary transistors should work OK.

-better to use two pots, one to adjust offset and second to adjust idle current through output stage. With 80mA of idle current, 4.7ohm emitter resistors and small heatsink, the bias should be stable.
 
Hi guys, thanks for the advice.


Ifrythings-

Do you mean the amplified diode setup? I was trying to keep the stage as simple as possible, so I didn't consider that type of approach. I was hoping the symmetry of the layout would give good thermal tracking.:rolleyes:



Darkfenriz-

It's going after a couple of tube eq stages.

The reason for the high supply voltages is that it's to go in the middle of a tube preamp, to drive a lo-z pultec style equalizer. I'm trying to make it integrate better with the hi-z/voltage stages that come before it.

The idea is to set the tube stages up so that they run out of headroom just before this transistor stage does.I am going to pad the signal slightly before this stage to make sure of that.The idea is that if clipping does occur, it won't be in a stage with lots of feedback, and rather in a triode. Not that I want any clipping, but it does happen sometimes.

I'll use a dual pot to adust the bias current.

About the 1st followers-you're right,that was a bit paranoid on my behalf. The 2sk389s have plenty of current to drive the output trannies.

The fets are currently set up to dissipate about 120mW each side, so 240mW for the chip. They are supposed to take 400mW. Am I running them a bit hot?I would consider maybe paralleling 2 of them if this is a problem.

I've never used these fets before. Since they are rated for 50v, I thought they would be fine at this voltage. Do they like more current and less voltage?


Thanks again
 
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it will surely work, but observe that the bias depends on the absolute supply voltage. That means that any variation of the supply, including ripple and noise, will turn up at the output. Your Power Supply Rejection Ratio is quite low, not a good thing for good sound quality.

An immediate improvement would be to replace the 10k pot with a string of diodes, that would increase the PSRR and also make it much less temp dependent (the diode tempco will partially offset the driver/output transistor tempco). Also, place a cap over the bias circuit to reduce supply influence.

Jan Didden
 
Hi Janneman,

I hadn't considered PSRR! :rolleyes: . How would the diode string improve this?

I intend to run it off a well regulated supply, and will have a few class A circuits hooked up to the same supply. Am I asking too much of the power supply?

The reason I decided to use the resistor is that i was worried about the diodes turning on and off at higher voltages.


Thanks for the help
 
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Joined 2002
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Well, the diodes would always be conducting, they would be between the two bases of the drivers and as such present a constant bias voltage. If the temp goes up, the transistor Vbe would go down, meaning the quiescent current would go up with potential runaway, but the diode voltage would also go down (assuming they have about the same temp as the transistors, depends on physical mounting) so this would somewhat stabilise the quiescent current.

I agree that a regulated PS would make the PSRR less of an issue, but the temp issue would remain and should not be underestimated.

Jan Didden
 
That's true, the diodes should conduct all the time, as long as there is current to supply them/voltage across them. I noticed them turning off in the simulation, the reason though was that I was starving the bias diodes of current, because there was only enough to supply the transistor's base. (Because the transistor has a lower threshold voltage?) My Bad:dead:

-I'm going with the diodes :), but with a small pot for offset adjustment.

Now at this stage I'm getting paraniod about thermal runaway:angel:

In the interests of thermal stability I've increased the emitter resistors to 47 ohm, because I don't need an output Z of 10 Ohms anyway.

Are these measures enough to produce good thermal stability?

I've been toying with the idea of using a CFP configuration for the output transistors, because there is not that much current flowing in the bias network. This should reduce distortion at higher signal levels.

My question is- Am I asking for trouble? People have mentioned oscillation problems with CFP devices, however I think they were common collector stages.
 

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I have used resistor biasing and diodes. They will both work well (the diodes may be the better choice). IIRC, I needed to wait 5 minutes (more really) after turning on the amp (on the bench) before taking measurements seriously.

Once while doing class AB, I recall the ouputs were cut off at turn on, yet would still runaway in time. Setting them up with lower bias still, was the key. They would hit a point of quiescent conduction and then settle. Heatsinks play an important part in this (of course).

Then if it passes load testing, it should survive in use.
 
Sorry, bad use of language.

Thanks alot for the advice guys. I don't have much hands on experience of solid state output stages, and really appreciate the input.

I was thinking about using CFP's because I need the extra gain to make things easier for the Jfet stage (the power dissipation limit on these devices only allows me to use 3-4mA of bias current at these voltage levels).

I was also trying to think of simple ways to improve the
thermal behaviour of the output stage, which is why I chose the CFP over the darlington.

The supply rails are going to be well regulated (easy to do because of low currents required ) so I imagine this will provide consistant enough Vbe for the driving BJTs to keep the bias conditions stable.

After looking through archived posts, I am concerned about the stability of the CFP now. I would probably have to build in some compensation.

People have reported that the they don't like the sound of CFP's over the emitter follower because of their tendency to oscillate. Maybe these were designed with a low phase margin in the interests of preserving speed? Maybe I be better off cascading 2 EF stages and avoiding all this?
 
I did some tests and reported on here, basically the extra swing available from CFP over EF is not worth worrying about. CFP does have a thermal advantage, but EF is not so bad really.

I personally like EF Type II output as characterised by Doug Self. CFP is OK but crossover behaviour of EF type stages is nicer (better for low level listening) and CFP you can't turn off as quick.
 
The CFP idea is dust.:) I just examined my priorities, and it doesn't provide any real advantage to me in practice except the thermal thing, which I gather is not really that much better than EF. 2 emitter followers it is.

I will just pay attention to layout and thermal mounting etc. I also have some decent sized heatsinks knocking about the place which will help.

Thanks again for the input
 
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