Simplicity and elegance, feedback wanted!

[BesPav]

Originally Posted by Hans Polak

First of all, a conditionally stable amp is the last thing we want, don’t we ?

Ok.
Noninverting unconditionally stable amp mostly anyway have different source resistances seen from its inputs. Now, just think, do it have equal voltage drop caused by input bias current? Do this drop equal to differential and common mode? Do this drop are equal through working signal voltage swing? Do this drop are equat through input common-mode range?


So, what amp do you want now?

Have no doubt, i'll prefer to keep amp inside known stability conditions and have +60 dB feedback handicap than use unconditionally stable miller-compensated first-order one.

[stinius]

Originally Posted by SSassen

I run the amplifier in balanced mode, which really is a requirement for me.

Why?

Your AC input source, is it floating? or does it have a ground reference?

[Ultima Thule]

I might be wrong and I don't have access to any simulator to check it, but here's how I see it, the protection circuit for the output FET stage doesn't work as one might think, those 2 transistors Q15, Q16, and 2 diodes D3, D4, supposed to sense the voltage fall over the source resistors at 0,1 Ohm in the occurrence of a short at the output do nothing, or, almost nothing, because as we will soon see they do "protect" but in a peculiar way.

The lower side of the Vbe multiplier circuit, which is biasing the output stage, is during positive cycle clamped to the output through lower over current protection transistors collector-base diode + lower diode + source-R (Q16 + D4 + R26).

And vice-verse during negative output voltage cycle, the higher side of the Vbe multiplier circuit is clamped to the output through the upper transistors collector-base diode + upper diode + source-R (Q15 + D3 + R24), hence these two transistors do not act on the voltage fall over output FET source resistors more than two passive diodes via their base-collector diode.

And the reason the output clips harder for positive cycle is because the N-ch FET's have lower Vgs threshold than P-ch FET's, in any case the Vgs drive is always so low due to the clamping that the output FET's becomes self limiting without any protection circuit.

To make the output protection circuit (consisting of Q15, Q16, D3 and D4) engage during a short, we would need at the very least some 0,6 Volt voltage fall for each of ALL 4 devices (Q15, Q16, D3 and D4), ie. 2,4 Volt, and 2,4V over R24 alone equals to 24 Ampere for one output device, which doesn't happen due to the clamping effect explained above, ie. the protection circuit doesn't work as expected.

[Mooly]

petr_2009

All your posts that are unrelated to this thread have been split off to here:

Musings on amp design... a thread split.

If you wish a different title then please report post #1 of the new thread and say what you want it to be called.

Please in future do not hijack and drag other established threads off topic as you have this one.

[MarsBravo]

Originally Posted by SSassen

Thanks! But these simulations fall apart when I run the amplifier in balanced mode, which really is a requirement for me.

SSassen, can you draw a rough sketch block diagram of your final 'balanced mode' application? I'm busy with a balanced bridge Hiraga with an unbalanced input, hence this question.


ps:
Good split Mooly!

[SSassen]

Originally Posted by MarsBravo

SSassen, can you draw a rough sketch block diagram of your final 'balanced mode' application? I'm busy with a balanced bridge Hiraga with an unbalanced input, hence this question.

Apologies for the late reply, work caught up with me ...

Not entirely sure what you mean, the schematic as posted shows the balanced mode operation, which only applies to the input really, the output of the amplifier is single ended.

[SSassen]

Originally Posted by bucks bunny

If you look at the amp as an operational differential amp, these things will matter imho. Resistor networks on inv and non-inv inputs should match precisely to yield max CMMRR - which translates to PSRR as well.

Yes, luckily we have commonly available 0.1% resistors that take will tackle this at reasonable cost.

[SSassen]

Originally Posted by Ultima Thule

I might be wrong and I don't have access to any simulator to check it, but here's how I see it, the protection circuit for the output FET stage doesn't work as one might think <snip>

petr_2009 was kind enough to simulate it here, so you won't have to take just my word for it, please see below quoted link.

Musings on amp design... a thread split.