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Just another lateral FET amp
Just another lateral FET amp
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Old 24th July 2019, 06:04 AM   #1
voltwide is offline voltwide  Ireland
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Default Just another lateral FET amp

I am starting this thread to present my latest amp design using Hitachi lateral FETs. This is a remake of my designs in the early 80s and born by a rare chance: Earlier this year an old friend of mine gave me a convolute of NOS 2SK135/2SJ50. This was the preferred technique in these days so I decided to do an update. Nowadays I design class-D amps with TI chips being much smarter in size and power consumption with impressive performance. So why re-vitalize this obsolete stuff?
Because there are applications where class-D sucks. And I am not talking about driving loudspeakers in Hi-Fi setups, this is a job they do fairly well. But measuring applications in a lab can be quite annoying with class-D output. For instance look at a small signal of let us say 1Vpp with an oscilloscope - you will not find it hidden in the switching residual.

Another point is full bridged output is not desirable in lab measurements, so the tradiditional split supplied half bridge topology is preferred.
These aspects gave enough excusions for me to fiddle around with another lateral FET amp
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Old 24th July 2019, 06:08 AM   #2
voltwide is offline voltwide  Ireland
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The starting point
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Old 24th July 2019, 06:19 AM   #3
voltwide is offline voltwide  Ireland
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Actually I am waiting for the pcbs of the first layout revision done with KiCAD.
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Old 24th July 2019, 06:29 AM   #4
voltwide is offline voltwide  Ireland
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For those interested in KiCAD I will post my sheets and libs as well, which may be helpful for the beginners. These libs include all my parts used, no need for any other libs.
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File Type: zip 00c_w_passives.pretty.zip (67.5 KB, 53 views)
File Type: zip 00.lib.zip (9.3 KB, 45 views)
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Old 24th July 2019, 02:13 PM   #5
nigelwright7557 is offline nigelwright7557  United Kingdom
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Quote:
Originally Posted by voltwide View Post
For instance look at a small signal of let us say 1Vpp with an oscilloscope - you will not find it hidden in the switching residual.
It depends on how well the output is filtered and how high the carrier frequency is.
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Old 24th July 2019, 02:24 PM   #6
voltwide is offline voltwide  Ireland
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It does, but with practical pwm frequencies of 400~600kHz there is not so much to be gained. And for wider bandwith applications the output filter is a no go.
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Old 24th July 2019, 04:29 PM   #7
voltwide is offline voltwide  Ireland
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Please replace "00c_w_passives.pretty.zip"
by
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Old 24th July 2019, 04:41 PM   #8
voltwide is offline voltwide  Ireland
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These are the actual schematics
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Old 24th July 2019, 06:18 PM   #9
voltwide is offline voltwide  Ireland
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I fiddled about 6 weeks with LTSpice to develop this circuit. The main goals were
-rocket solid design
-power bandwidth >100kHz
-very low THD upto 20kHz ↔ >60dB gain upto several 10kHz
-high CMMR
->40Vpp into 8 Ohms
-asymmetric input, Z>10kOhms
-components available at Mouser (excl latFETs)


Some Circuit Details -The LTP

There is nothing really special here. The current source driven by a voltage reference yields high CMMR.


The VAS

To achieve max speed the cascode configuration is mandatory. Even in cascode configuration BJTs like BD139/140 or MJE340/350 restrict bandwith as well as linearity (early effect). Best results are obtained with fast low voltage types like BC550/BC560 or BC546/556 respectively. For higher supply voltages the derivates of 2N5551/5401 seem to be the next best choice. An active current mirror between differential input pair and VAS provides additional loop gain which is beneficial over the hole frequency range.



Gate Drive Buffer

A complementary emitter follower connects the VAS to the gates of the power MOSFETs. This reduces capacitive loading of the VAS stage and and improves loop stability as well. In the simulations it shows up as a significant improvement of THD specially at higher frequencies.



Slew Rate and Power Bandwidth

These are directly correlated to each other. Here are two bottlenecks that will limit the maximum available voltage slew rate.
1. LTP output charges the miller capacitance. Assume the differential collector current is biased to 2*1mA yielding a max charging current of +/-1mA and a 10pF Miller capacitance. The resulting slewrate is limited to SLR = I/C = e-3/e-11 = e+8 = 100V/us

2. The VAS provides limited current to charge the VAS loading capacitance. Assuming a VAS bias current of 10mA loaded by 100pF this results in

SLR= e-2/e-10 = e+8 = 100V/us

These numbers might give an idea of the practical SLR limits. So aiming at highest slewrate means


- minimize Miller capacitance

- minimize VAS loading capacitance

- maximize VAS bias current

Output Stage

Actually no snubber, no series inductors, no damping resistors. All these things removed that restrict a wideband output. No risk, no fun!
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Last edited by voltwide; 24th July 2019 at 06:27 PM.
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Old 24th July 2019, 08:57 PM   #10
Tournesol is offline Tournesol  Belgium
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Nice VFA, Voltwide. I like the current mirror.
Just a question, how are-you going to cool the HEXFETS ?
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