Marshall Leach's RIAA preamp (1977) looks like a low power version of this amplifier, with only a single output transistor stage, and is similar to the circuit posted by gannaji, but the main difference to both are the addition of the current mirror to increase OLG and reduce distortion.
I can only say that this is an incremental change, I haven't seen the 1979 preamp, but the mirror technique was used in Bob Cordell's '83 design. So I agree the concepts are not new.
The differential driver concept was, as mentioned, in Mullard's 1973 book, which was where this design was based.
All I've done is to swap the NPN diff VAS for a PNP and add the differential input with the current mirrors. An evolution perhaps, not a revolution.
I can only say that this is an incremental change, I haven't seen the 1979 preamp, but the mirror technique was used in Bob Cordell's '83 design. So I agree the concepts are not new.
The differential driver concept was, as mentioned, in Mullard's 1973 book, which was where this design was based.
All I've done is to swap the NPN diff VAS for a PNP and add the differential input with the current mirrors. An evolution perhaps, not a revolution.
I am not too worried about the source of circuits and combinations of architecture as long as they work.
I have seen the photo of your 'scope but no .asc file or .raw files have been posted.
The image of the schematic that you did post was with a simple sine wave at 1kHz and you have quoted THD results we don't know if the two circuits tested were the same.
Look more carefully!
The measured distortion signal (the only harmoinc clearly visible) showed a frequency of 3925Hz. THe test signal was a nominal 2kHz.
The resistor colour codes on the PCB should match the diagram except I may have used a 6.8k instead of 5.6k. The 0.5 ohm resistors are two 1 ohm in parallel.
I'm sure anyone can duplicate the .asc file from the circuit if they wish using LTspice. I have not used LTspice to simulate the distortion - the diagram was only my first attempt in LTspice!
(The reason for using 2kHz instead of 1kHz is simply to ensure the fundamental frequency is visible on a suitable scale on the analyser).
(I could post an .asc file once I have confirmed a distortion result in LTspice. Until I'm happy with that, not).
The measured distortion signal (the only harmoinc clearly visible) showed a frequency of 3925Hz. THe test signal was a nominal 2kHz.
The resistor colour codes on the PCB should match the diagram except I may have used a 6.8k instead of 5.6k. The 0.5 ohm resistors are two 1 ohm in parallel.
I'm sure anyone can duplicate the .asc file from the circuit if they wish using LTspice. I have not used LTspice to simulate the distortion - the diagram was only my first attempt in LTspice!
(The reason for using 2kHz instead of 1kHz is simply to ensure the fundamental frequency is visible on a suitable scale on the analyser).
(I could post an .asc file once I have confirmed a distortion result in LTspice. Until I'm happy with that, not).
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Does anybody have a link to an explaination on how this Cordell's current mirror trick works ?
Thanks
You are probably familiar with the simple transistor current sensing constant current source (see diagram).Tr2 senses the current in Tr1 and keeps the current in Tr1 constant.
Now imagine two CCS transistors (tr3 and Tr5). If the currents in these are equal the voltages across the bases of the sense transistors (Tr4, Tr6) will be the same. So they can be joined. Now if the current in one of the CCS transistors (e.g.Tr5) increases, that will raise the base voltages, so the sense transistors turn on more. As a result they will try to reduce the current (in both) but as they share the common base, that keeps the combined current in Tr3 and Tr5 constant.
The base resistors in Tr4, Tr6 are necessary to allow the CCS transistors to swing to different currents. So they are not really CCS's but a true differential with the combined current kept constant.
The connection between the two bases (Tr4, Tr6) measures the average voltage across the two output transistors (Tr3, Tr5) through the shared connection. The other point to note is that the current into the sense side is fixed (by the previous differential stage) and that sets the base voltage, hence keeping the average voltage constant.
In practice the sense transistors usually have emitter resistors to increase the voltage drop across the resistors which set the current.
I don't know how BOb explains it but this might help.
I don't know when this circuit was first used but it seems to be common in IC design.
Now imagine two CCS transistors (tr3 and Tr5). If the currents in these are equal the voltages across the bases of the sense transistors (Tr4, Tr6) will be the same. So they can be joined. Now if the current in one of the CCS transistors (e.g.Tr5) increases, that will raise the base voltages, so the sense transistors turn on more. As a result they will try to reduce the current (in both) but as they share the common base, that keeps the combined current in Tr3 and Tr5 constant.
The base resistors in Tr4, Tr6 are necessary to allow the CCS transistors to swing to different currents. So they are not really CCS's but a true differential with the combined current kept constant.
The connection between the two bases (Tr4, Tr6) measures the average voltage across the two output transistors (Tr3, Tr5) through the shared connection. The other point to note is that the current into the sense side is fixed (by the previous differential stage) and that sets the base voltage, hence keeping the average voltage constant.
In practice the sense transistors usually have emitter resistors to increase the voltage drop across the resistors which set the current.
I don't know how BOb explains it but this might help.
I don't know when this circuit was first used but it seems to be common in IC design.
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You did quote some simulated figures in post 1 and someone asked if you would make the .asc file available which drew no response and from what you are saying now this is still up in the air.
Not everyone who may be interested in this circuit would be able to draw up a simulation and others in the know, who may not have the time to spare to do so.
I had drawn up a simulation for THD at 15 W into 8R at 20 kHz and the indicated only results were exemplary 0.006% and 0.002% at 1 W.
I will get back when I have run a Tian probe test.
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Dear Mjona,
Please post your .asc files along with the commands and models to help learners like me as a learning exercise to hone our skills.
--gannaji
There is an alternative Tian Probe Test that gives a better result than this. I downloaded a simulation of the V-Hex -OIPC amplifier by dadod who has a high profile with solid state design.
You might have to do a bit of detective work to find this. I feel it would be breach of ethics to post dadod's .asc file here and for me to butt-in by posting mine.
Finally persuaded LTspice to run a Tian probe. Mjona, you hinted it would be better. Shows a bigger phase margin. Still haven't got to grips with all the nuances of LTspice yet, tried latest release but wouldn't pick up the BD139 models from the (edited) bjt lib, so this is in version IV.
However, like all simulations the stability issue is only a guide. My concern for large signal amplifiers is that, well, the transistors operate in large signals and the parameters change quite significantly over the operating range. Tian probes etc only pick the DC conditions at the time and don't cover this range.
It's the old saying - if a (any) small signal simulation shows instability, it is probably right. If it does not, it is not a guaranteed proof of stability.
However, like all simulations the stability issue is only a guide. My concern for large signal amplifiers is that, well, the transistors operate in large signals and the parameters change quite significantly over the operating range. Tian probes etc only pick the DC conditions at the time and don't cover this range.
It's the old saying - if a (any) small signal simulation shows instability, it is probably right. If it does not, it is not a guaranteed proof of stability.
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If your amplifier puts out full clipping at say 1 volt, run the stability analysis with a swept DC “bias” from - to + 1 volt. You will have to disable (short) the input and feedback blocking caps to give it full gain down to DC. Run these analyses over a range of load. To sort of capture the effect of a reactive load, hang a current source of half the peak current from the output to the rail and repeat for each rail/polarity. If you see any strange jumps in behavior, run a finer sweep between the two points where the jump occurred. This won’t capture “pumped” oscillations, but they are far less common in audio than they are at RF. It will find the stuff that kicks in on one little part of the negative half cycle, for example, though. If your models are good enough.
A series of small signals around the range of DC operating points would be useful I agree. Transient is still preferable to find, as you say, pumped oscillations as it usually does so pretty quickly. The differences in phase margin could be due to model differences, in fact probably is as I used LTspice's main lib. instead of my default lib.
I'd still be concerned that at high frequencies stored charges in the opposite transistor will be missed.
I'd still be concerned that at high frequencies stored charges in the opposite transistor will be missed.
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Wow! That was quick, thanks Prasi.
I do have to offer a couple of suggestions, which I hate to say would cause a bit of layout change (if implemented).
If using modern high speed transistors like the MJL4281 then the compensation capacitor should be reduced. I think this would be around 2.2pF, but you have allowed for some options there. (2.2p can be made by twisting a couple of plastic insulated wires together about 50mm long, or even a small double sided PCB plate I've used before). Needs some evaluation. More simulation - and checking. I have a pair of MJL3281A's mounted on a similar heatsink, so that might be possible fairly quickly.
Secondly, the gain variation in the output transistors may need some adjustment in the diff. pair. If using the MJL4281 then this is a high gain device and may not need adjustment. I did suggest in one of the posts to use a pot. in the diff. pair. A (physically) small pot (perhaps 2.2k) in series with 1k replacing R23 would be my recommendation. Of course, it would be possible to select R23 on test without changing the layout.
Note - the emitter resistors should be 1 ohm, not 0.5! (Paralleled to make 0.5).
I do have to offer a couple of suggestions, which I hate to say would cause a bit of layout change (if implemented).
If using modern high speed transistors like the MJL4281 then the compensation capacitor should be reduced. I think this would be around 2.2pF, but you have allowed for some options there. (2.2p can be made by twisting a couple of plastic insulated wires together about 50mm long, or even a small double sided PCB plate I've used before). Needs some evaluation. More simulation - and checking. I have a pair of MJL3281A's mounted on a similar heatsink, so that might be possible fairly quickly.
Secondly, the gain variation in the output transistors may need some adjustment in the diff. pair. If using the MJL4281 then this is a high gain device and may not need adjustment. I did suggest in one of the posts to use a pot. in the diff. pair. A (physically) small pot (perhaps 2.2k) in series with 1k replacing R23 would be my recommendation. Of course, it would be possible to select R23 on test without changing the layout.
Note - the emitter resistors should be 1 ohm, not 0.5! (Paralleled to make 0.5).
I've run a sim using MJL3281A output transistors. 22pF is confirmed unstable. Optimum is 4.7pF as is, but phase margin is very low.
Solution is to add two 100pF "sprog stopper" capacitors between the base and collector of the driver transistors (BD139's) and then the feedback capacitor can be kept at 22pF, to give a phase margin somewhat better than the 2N3055 (in my original simulator) (~ 50 degrees).
Solution is to add two 100pF "sprog stopper" capacitors between the base and collector of the driver transistors (BD139's) and then the feedback capacitor can be kept at 22pF, to give a phase margin somewhat better than the 2N3055 (in my original simulator) (~ 50 degrees).
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